File handling of XML and YAML format in System Verilog

SystemVerilog
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Hi Folks,

I have got some doubts in File Handling in System Verilog.

I am using File handling in my UVM code. The file content which I am reading inside my sequence is a normal text format file (.txt file).
Its working fine.

My question is Does SV supports file handling of XML or YAML format files. If yes can you give an example

Thanks,
Yogaraj

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In reply to Yogaraj Selvalingam:

SV doesn’t have any special provision for reading xml files, SV supports ASCII file reading/writing. One way I have used in similar problems is to devlop an python/perl script which parses the xml files and dump the data into a file in simpler format of key value pair. Then parse this generated file using $fscanf or $fgets. To support runtime conversion you can call this script from env itself using $system.

-Rohit

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In reply to Yogaraj Selvalingam:

The ‘svlib’ Utility Library that Verilab made has a toolkit that provides YAML support. You check to see if that has what you need.

Disclaimer : I’m not part of Verilab nor have I specifically used YAML portions of their tool library. So Caveat Emptor