Evaluate each line in a file in systemverilog

SystemVerilog
,
1

I’d like to parse lines inside file1.txt in the load_reg() function below.

file1.txt contain 2 lines:


reg1 = 1;
reg2 = 2;



class A;
  reg1 = 100;
  reg2 = 200;
  function void load_reg();
    // open file1.txt and parse them
  endfunction
endclass

The intention is to make reg1 and reg2 become 1 and 2, when load_reg function is called.

I’m aware that `include would work, but file.txt path is dependent on environment variable, and thus it’s impossible (correct me if i’m wrong) to implement something like


string path = {getenv("FILE1_PATH"), "/file1.txt"};
`include path

Please assist.

2

In reply to warlocklw:

Unlike interpretive languages like Python or PERL, it’s very difficult to parse and execute code for compiled languages like SystemVerilog once the compiled code starts executing. It’s not impossible, but it would be much easier to pass the include file path to the compiler

setenv FILE1_PATH /u/mydir
compile_command source.sv +define+FILE1_PATH=$FILE1_PATH

Then in your source

`define qconcat(s1,s2) `"s1``s2`"

function void load_reg();
    `include `qconcat(`FILE1_PATH, /file1.txt) // Note: do not use quotes here, they are added by `qconcat
endfunction

Note that some tools will expand environment variables in `include file paths with the right options. Check your tool’s manual.

`include "$FILE_PATH/file1.txt"