Error in using define for struct

SystemVerilog
,
1

for code-

module type_def;

typedef struct {int i;} tps;
`define dps struct {int i;};

initial begin
tps p1,p2;
`dps p3;
end

endmodule

I am getting following error-
type_def.sv(8): near “;”: syntax error, unexpected ‘;’, expecting '(

I cant understand the reason for it.

2

Please use SystemVerilog tags around your code(I added them for you), and I assume line 8 was

`dps p3;

It would have helped if you pointed that out.

The reason for the syntax error is the extra semicolon at the end of your **define dps**. The becomes part of the text replaced by dps.

3

In reply to dave_59:

Thanks dave_59. I will remember tags next time.