Hi ,
I was trying the following code ::
bit [6:0] ip = 1 ;
bit [7:0] op ;
clocking cb @(posedge clk);
default input #1 output #2;
output op ;
input ip ;
endclocking
bit clk ;
always #5 clk = ~clk;
mult_if inf( clk );
`define TB_IF inf.cb
initial begin
// Drive Exactly on 1st posedge of clk !!
@( cb ) ;
cb.op <= cb.ip + 1 ;
$display(" Output clockvars \"op\" driven %0d at TIME : %2t " , ( cb.ip + 1 ) , $time );
end
always @( op ) $display(" Raw Signal \"op\" changed to %2d at T:%2t " , op , $time );
initial #20 $finish() ; How is it that the raw signal ' op ' is driven on same clocking event relative to output skew of #2 units i.e at time: 7 units?
By the time @( cb ) unblocks the posedge of clock has already occurred , so my expectation was it would be driven at next posedge of clock ( relative to output skew )
i.e at time 17 units .
Instead of @( cb ) if I were to write #5 OR @( posedge clk ) , I observe the same output i.e always block is triggered at time 7 units
I expected the behavior would be similar to :
Driving between 2 clocking events results in the output clockvar being driven at the next clocking event
Eg : If I were to drive at time 10 units , the raw signal would actually be driven on next posedge of clock at time : 17 units
