Driving output clockvars on clocking block event

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Hi Ben ,
Yes I do agree that using clocking blocks , net type can be driven procedurally through class type via a virtual interface .

However the confusion I have is regarding driving output clockvars on exactly the posedge of clk via any of the 3 ways above

Why is it being driven on same clocking event and not the next one since @( cb ) unblocks after posedge of clk occurs ( due to loopback from observed to active region )

I drive exactly on @( cb ) / @( posedge clk ) since my driver component would be


  seq_item_port.get_next_item( req );

  @( vif_intf.cb );

    vif_intf.output_clockvar  <=  req.property ;

    ...................