Discrepancy with int Cast

SystemVerilog
,
1

Hi Forum ,

I have following Code ::


class ADD ;
  
    rand bit [30:0] a[2]  ;
 
    constraint SUMM { a.sum with ( int'(item) )  == 32'd2**32-2 ; }  // Would it Pass ??
 
endclass 
 
ADD obj ;
 
initial begin
 
   obj = new() ;
  
  repeat(2)
  if ( obj.randomize()  ) 
    $display("Success with %p",obj); 
  else
    $display("Fails");
end

I Observe different Output across Simulators ::

SIMULATOR1_FAILS whereas it passes with Other Simulators ( Run with different Simulator on EDAPlayground )

[ Although the Other Simulators are older version I actually Observe Same results with their respective Licensed Simulators @ work ]

I believe some implementation uses a Sign Extension ( 31st bit is Duplicated ) leading to failure

Please note that my intention isn’t to discuss Simulator Issues


LRM 7.12.3  says  ::  "When specified, the with clause is used to determine the type of the result.
                       Casting item to an int in the with clause causes the array elements to be extended to 32 bits before being summed.
                       The result of calling sum in this example is 32 bits since the width of the reduction method result 
                       shall be the same as the width of the expression in the with clause"

My Understanding is to achieve 32-bits ::

(1) 0-Padding Should take place ( if each element is smaller than 32-bits ) if the element is Unsigned type ( bit / logic )

**(2) Sign Extension Should take place ( if each element is smaller than 32-bits ) if the element is Signed type ( bit signed / byte )
**

[Q1] Agree OR Disagree with (1) and (2) ??

[Q2] I believe Randomization Should have Passed in the Code above !!

i.e I Should Observe a:'{'h7fffffff, 'h7fffffff}

2

In reply to TC_2017:

This is the same issue you brought up in Signed Arithmetic in Constraints | Verification Academy

3

In reply to dave_59:

Hi Dave ,

Yes I did bring this up in int’()/32’() Cast

Similar to the Semaphore thread which was discussed yesterday , I believe the LRM isn’t clear on whether int’() Cast is a Signed Addition .

The reason I brought it up again is that to discuss the 0-Padding VS Sign Extension condition for elements .

4

Refer LRM 6.24.1


   int'( expr1 )  is Same as 
   int  temp1 ;
  
   temp1 = expr1 ;

So essentially in the Original Code each item is a signed element of 32-bits ( int type )

Hence the Max Sum() Should be 31 bits via int’() Cast .

Better to do 32’() Cast where you achieve sum up to full range of 32-bits


 LRM 6.24.1 ::  
When changing the size, the cast shall return the value that a packed array type with a single [n-1:0] dimension would hold after being assigned the expression, where n is the cast size.
The signedness shall pass through unchanged, i.e., the signedness of the result shall be the self-determined signedness of the expression inside the cast.

**Therefore via 32’( item ) your points (1) and (2) would be Applicable i.e

The signedness of the expression would depend on the element type**