CROSS COVERAGE

SystemVerilog
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1

Hi,

As i am new to coverage i would like to know whether my approach is correct or not!
i have following signals and i want to cross all of them to check respective modes are covered or not.

logic [3:0] mode;
logic [4:0] sif_reg;
logic [4:0] mem;
logic b;
logic bypass;
logic sif_load;

c_m: coverpoint mode {
      bins md1= {4'b0000};
      bins md2 ={4'b0001}; }
c_sif_reg: coverpoint sif_reg {
       bins sif_reg1= {5'b11111};
       bins sif_reg2= {5'b00101}; }
c_mem: coverpoint mem {
       bins rom={5'b00001};
       bins ram={5'b00010};
       bins rf={5'b00100} }
c_b:coverpoint b{
      bins low={0};
      bins high={1}; }
c_bypass:coverpoint bypass{
      bins low={0};
      bins high={1}; }
c_sif_load: sif_load {
      bins low={0};
      bins high={1}; }

cross_all: cross c_sif_load, c_bypass, c_b, c_mem, c_m, c_sif_reg {
             bins mode1= binsof(c_m.md2) && binsof (c_sif_reg.sif_reg1) && binsof(c_b.low) && binsof(bypass.low);
             bins mode2= binsof(c_m.md1) && binsof(c_sif_reg) && bisnof(b) && binsof(c_mem) intersect {5'b11111};
             bins mode3= binsof(c_m) && binsof(c_sif_reg) && bisnof(c_b) && binsof(c_mem); 
             bins mode4= binsof(c_m) && binsof(c_sif_reg) && bisnof(c_b) && !binsof(c_mem) intersect {5'b00000};
             }

1.For mode1 i missed binsof(c_mem) though i mentioned in cross, in this case will it take default or it will not consider?
2For model2 i was used binsof(c_mem) intersect {5’b11111} which is i didnt declared as bins in respective coverpoint, how
this will take?
3. for mode3 i am using only coverpoints in binsof, for this how many combinations it will take
4. for mode4,can i write like this to select all combinations of mem except rom (5’b00000) with abw combinations?

                                        Thanks in Advance
2

In reply to kathula venkatesh:

When crossing coverpoints, cross bins for all combinations of coverpoint bins in the cross get created. So you start with 22322*2 = 94 automatically generated cross bins. The bin specification is used to merge or eliminate bins in the cross. The bin specification describes a set of matching value to include in the selection.

The mode1 section matches 3 bins since you did not include c_mem. It is like a don’t care. Those 3 bins get merged into the bin mode1.

binsof(c_mem) intersect {5’b11111} match no bins of c_mem, so the mode2 bin will be empty/eliminated.

mode3 matches all 96 bins, so they all get collpased into a single bin.

binsof(c_mem) intersect {5’b00000} also matches no bins of c_mem, so the negation of that matches all the bins, so again all 96 bins get collapsed into one.

3

In reply to dave_59:

Thanks a lot Dave,
May i know the difference between crossing coverpoint lables and crossing variables?
For example
1.cross c_sif_load, c_bypass, c_b, c_mem, c_m, c_sif_reg; (222322) bins ?
2. cross sif_load, bypass, b, mem, mode, sif_reg; (222321632) bins ?

1.If we mention coverpoint or coverpoint label in cross will it take only explicit bins created in that coverpoint for cross coverage automatic bins?
2. if we mention variable in cross will it take all possible combinations during cross coverage automatic bins?

4

In reply to dave_59:

Hi Dave,
I don’t fully understand this line
“mode3 matches all 96 bins, so they all get collpased into a single bin”

Can you please elaborate this?

Thanks and regards,
Parvez

5

In reply to Parvez:

You are correct about the difference between crossing coverpoint labels and crossing variables. When you cross a variable directly, an implicit coverpoint gets created with the default maximum of 64 bins spread across the value range.

For mode3, the cross takes each automatically generated bin and checks if it intersects with the select expression. If it does, the automatically generated bin is removed. mode3’s select expression matches everything, so all of the auto-generated bins get removed. This is all explained in section 19.6.1 Defining cross coverage bins of the IEEE 1800-2017 SystemVerilog LRM

6

In reply to dave_59:

Thanks a lot David