Contraint with 'int unsigned" random variables seem to generate negative numbers

SystemVerilog
,
1

I have a simple constraint in my code that looks like follows:

class my_class;
rand int unsigned a, b, c;

constraint abc_constraint { (a + b + c) == 100; };
endclass

when I randomize the class and print the three constrained variables and their sum, I always get the sum to equal 100 (as it should) but some of the three variables randomize to negative values even though they are declared as ‘int unsigned’. For example, here’s one of the randomized value:

a = 1620722366, b = 3610665197, c = 3358547129, sum = 100

Can someone shed a light on why this is?

I am using Questa 2021.3

Thanks!

2

In reply to Earthling:

These are not negative numbers, just very large positive numbers that overflowed when added together. See Verilog Basics for SystemVerilog Constrained Random Verification which was derived from my DVCon 2020 paper.

3

In reply to dave_59:

Thanks Dave! It makes much more sense now.