Constraints on array elements

SystemVerilog
,
1

I am looking for an optimized solution for a constraint on array elements . For instance if we want the array elements of a dynamic array to be in descending order a foreach as shown below will work fine for smaller arrays but is there a more efficient solution ? How can we write up constraints that can target each element of an array ?

eg. to get the array elements to be in descending order

class dyn_array;
rand int abc;
constraint abc_descending_c{
abc.size() == 5;
foreach(abc[i]) begin
abc[i] > abc[i+1];
end

}
endclass

2

In reply to pkumar16:

Minor change:
class dyn_array;
rand int abc;
constraint abc_descending_c{
abc.size() == 5;
foreach(abc[i]) begin
if(i!=abc.size()-1)// to make sure abc[5] doesnt get accessed
abc[i] > abc[i+1];
end
}
endclass

I also tried this code :

class dyn_arr; 
  rand int abc[];
  constraint abc_c { 
    abc.size()==5;
   } 
  function post_randomize(); 
    abc=abc.rsort(); 
  endfunction 
endclass

but I am getting this error : $unit, “abc.rsort”
The call to predefined void function is not allowed in this context.
Cannot use a void function call where an expression is required

not sure why ?

3

In reply to verif_gal:

class dyn_arr; 
  rand int abc[];
  constraint abc_c { 
    abc.size()==5;
    unique {abc};
   } 
  function void post_randomize(); 
    abc.rsort(); 
  endfunction 
endclass
4

In reply to dave_59:

Thanks Dave!!