Constraint sum overflow

SystemVerilog
1 
module abc;
  
  class a;
    rand int unsigned aa;
    rand int unsigned bb;
    
    constraint c2 {
      aa + bb <= 10;
    }
    
  endclass
  
  initial begin
    a a1 = new();
    a1.randomize();
    $display(a1.aa, a1.bb);
  end 
  
  
endmodule

if I use the ‘int’ datatype, the sum is overflowing and the aa & bb are assigned with bigger values. Is there any solution to constraint aa & bb lessthan 10?

2

In reply to yourcheers:

plz add below things to constraint


 constraint c2 {
      aa >= 0; bb >= 0; aa < 10; bb < 10;
      aa + bb <= 10;
    }
3

In reply to Desam:

You can simply make the addition include the overflow bit instead of having it truncated.

module abc;
  class a;
    rand int unsigned aa;
    rand int unsigned bb;

    constraint c2 {
      33'(aa + bb) <= 10;
    }
  endclass
 
  a a1 = new();
  initial begin
    a1.randomize();
    $display(a1.aa,,a1.bb);
  end 
endmodule

Also see my DVCon2020 presentation on Verilog expression in SystemVerilog constraints.