I am trying to write a constraint such that dst_addr > src_addr+length or dst_addr+length < src_addr, but the below constraint is not working. That means dst_addr should never be in the range of src_addr+length and there should be enough space between dst_addr and src_addr that all the data can transferred from src to dst. dst_addr can be smaller than or greater than src_addr but the absolute difference between two should be greater than or equal to the length.
class trans;
rand bit [7:0] src_addr;
rand bit [7:0] dst_addr;
rand bit [7:0] length;
constraint c1 {! ( dst_addr inside {[src_addr:src_addr+length]}) && ! (src_addr inside {[dst_addr:dst_addr+length]} );}
endclass
module tb;
trans t;
initial begin
t = new;
repeat (30)
begin
t.randomize;
$display(t.src_addr);
$display(t.dst_addr);
$display(t.length);
$display("END");
end
end
endmodule
Thanks Dave I think it is working perfectly fine with added constraint.
values just with c1;
class trans;
rand bit [7:0] src_addr;
rand bit [7:0] dst_addr;
rand bit [7:0] length;
constraint c1 {! ( dst_addr inside {[src_addr:src_addr+length]}) && ! (src_addr inside {[dst_addr:dst_addr+length]} );}
endclass
module tb;
trans t;
initial begin
t = new;
repeat (30)
begin
t.randomize;
$display(t.src_addr);
$display(t.dst_addr);
$display(t.length);
$display("END");
end
end
endmodule
149
236
14
END
230
5
162
END
160
202
31
END
202
102
96
END
38
224
178
END
215
44
41
END
103//src_addr
93//dst_addr
189//length
END //In this particular case the difference between the |dst_addr - src_addr| >= length but the difference is 10
101
237
67
END
209
119
17
END
168 //src_addr
160 //dst_addr
115 //length
END //In this particular case the difference between the |dst_addr - src_addr| >= length but the difference is 8
79 //src_addr
130 // dst_addr
221 //length
END //In this particular case the difference between the |dst_addr - src_addr| >= length but the difference is 51
65
244
153
END
96 //src_addr
96 //dst_addr
180 //length
END // This is also not working as per expected
98
135
200
END
145
123
181
END
223
167
39
END
222
38
2
END
225
136
58
END
33
199
153
END
5
248
128
END
56
253
94
END
75
196
48
END
255
43
196
END
109
129
5
END
208
225
131
END
234
33
33
END
67
198
70
END
127
57
241
END
242
214
109
END
6
255
240
END
With the fix constraint c1 and c2: It works perfectly fine, with the above constraint numbers it is less intuitive that I might be missing the overflow condition.
Thanks now it is working.
class trans;
rand bit [7:0] src_addr;
rand bit [7:0] dst_addr;
rand bit [7:0] length;
constraint c1 {! ( dst_addr inside {[src_addr:src_addr+length]}) && ! (src_addr inside {[dst_addr:dst_addr+length]} );}
constraint c2 { 9'(src_addr+ length) < 256; 9'(dst_addr+ length) < 256;}
endclass
module tb;
trans t;
initial begin
t = new;
repeat (30)
begin
t.randomize;
$display(t.src_addr);
$display(t.dst_addr);
$display(t.length);
$display("END");
end
end
endmodule