Constraint to make signal for known clock cycles

SystemVerilog
1

How to write constraint for a given scenario?

signal should be high for 10 clock cycles then that signal should be low for remaining cycles.

2

In reply to v_govardhan:

Your question needs more detail. Is this constraint for checking the signal or generating the signal? When does the 1st of 10 clock cycles start?

3

In reply to v_govardhan:

How to write constraint for a given scenario?
signal should be high for 10 clock cycles then that signal should be low for remaining cycles.

Does it have to be a constraint?
Can you do something like:


class c; 
  virtual interface counter_if.drvr_if_mp vif;

  task automatic t10 (bit a, clk);
    repeat(10) @(posedge clk) a = 1'b1;
    forever @(posedge clk) a = 1'b0;
  endtask

  task automatic t10_interface ();
    repeat(10) @(this.vif.driver_cb) this.vif.driver_cb.a <= 1'b1;   
    forever    @(this.vif.driver_cb) this.vif.driver_cb.a <= 1'b1;
  endtask
endclass

module m; 
  bit a, clk; 
  initial begin 
    repeat(10) @(posedge clk) a <= 1'b1;
    forever @(posedge clk) a <= 1'b0;
  end
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  2. Free books: Component Design by Example https://rb.gy/9tcbhl
    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers:
4

Thank you for your response
I actually want to write constraint.
I have a variable called “enable”. I need to randomize this variable for 10 times.
I want to write constraint like enable should be high for only 10 times then it should be low.
can you help to write constraint for this?

5

In reply to v_govardhan:

What you are asking is not random at all. It can be dealt with in pre_randomize without any constraints.

class A;
  bit enable = 1;
  int counter = 10;
  function void pre_randomize();
    enable = --counter > 0;
  endfunction 
endclass