Compile checker in systemverilog

SystemVerilog
,
1

Hello there!

What’s the right methodology to put the checker in the compilation scope in SystemVerilog?

I have a tb_top.sv module where I’ve instantiated an instance of the checker.


module tb_top();
    // some other stuff
    checker0 i_checker0 (.clk(clk), .rst(reset));
endmodule: tb_top

I’ve placed the checker description in another file checker0.sv.


checker checker0 (input event clk, logic rst);
  //some assertions
endchecker: checker0

Then i compile both files,

vlog checker0.sv tb_top.sv

but at the end I get an error:

# ** Error: ../tb/tb_top.sv(2): Module 'checker0' is not defined.

So my question is:
What is the right methodology to include the checker in the compilation scope of SV?

Thank you for the input you can provide !

2

In reply to stefaniecg:

By default, each file that you compile on the command line is a separate compilation unit (same as other programming languages like C/C++). You would need to `include the file into your the tb_top.sv file to get it into the sample compilation unit.

We strongly recommend putting checkers in a package and importing that package where needed.

3

In reply to dave_59:

A checkers package is the way to go.
Thank you for drooping some knowledge!