Code within always @* in a generate doesn't inherit the generate for if (PARAMS) statement

SystemVerilog
, ,
1

I see compile issues with most of the vendors for this pseudo code (Simplified version):


generate 
if (PARAM1 == 1) then
  always @*
  begin
     if (PARAM2 == 1)
     begin
         sig2 = sig1[PARAM2+Width:Width+1]  //Compile error line
     end 
  end
end
endgenerate

It says that the bit slice is reversed for sig1. With PARAM1 = 1 , PARAM2 = 0 settings
The Compile Error Line shouldn’t be compiled for the above settings in the first place.

2

In reply to galavish:

The second
if (PARAM2 == 1) is a procedural-if, not a generate-if. So the code needs to compile even though it may never execute.

You’ll need to explain better what you are trying to do because it seems you should just use
sig1[Width+1]