Checks needed before a System Verilog IP sign off

SystemVerilog
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1

Hi Guys,

What are the standard checks we do before we sign-off a System Verilog IP?
Please comment if any one knows for Verilog or Mixed language IP also.
For ex:

If we have a IP(System Verilog RTL), what are all the checks we need to done before we handover to customer. My point of vie i Know few things listed below

→ Port names and bus widths will be verified at all instances
→ all inputs are connected or floating
→ include files are compiled before they use or not.

Like these Could you please suggests any other checks we need to do for a System Verilog IP or Mixed language(SV,Verilog,VHDL) IP?

Thanks,
Murali