Checking asynchronous reset whilst a signal is asserted

SystemVerilog
, ,
1

Hi,

I have just started incorporating cover points, cover-directives into the code whilst writing RTL.

There is a functional check I came up with to test asynchronous reset.

The scenario is:

  1. Is tvalid (AXI streaming) asserted (registered output w.r.t posedge of the clock)?
  2. Is asynchronous reset (active low) de-asserted?
  3. Is tvalid de-asserted?

This check ensures the asynchronous reset happened mid-packet and it ensures tvalid is grounded after async reset happens.

The sequence I came up with is

sequence seq_reset_n_check(tvalid);
@(posedge clk) tvalid ##1 @(negedge reset_n) ##1 @(posedge clk) !tvalid[*3];
endsequence

This doesn’t seem to work. I must admit, I don’t really know how the sampling is working here with multiple sensitivities.

Any help will be appreciated

2

In reply to ak180:

What you have is a sequence declaration.
@(posedge clk) tvalid ##1 @(negedge reset_n) 1’b1 ##1 @(posedge clk) !tvalid[*3];
Here you have 3 clocking events.
When that sequence is executed in an assertion directive, it says
@(posedge clk) tvalid // sampled value of tvalid ==1.
Then, @(negedge reset_n) ##1 // true. Then
@ next(posedge clk) !tvalid[*3];
As in any assertion, sampling is done in the Preponed Region of the clocking event, thus just before the event.

Show us the assertion directive. By itself, the sequence declaration does nothing. It’s a declaration, not a directive.
Ben systemverilog.us

3

In reply to ben@SystemVerilog.us:

In reply to ak180:
What you have is a sequence declaration.
@(posedge clk) tvalid ##1 @(negedge reset_n) 1’b1 ##1 @(posedge clk) !tvalid[*3];
Here you have 3 clocking events.
When that sequence is executed in an assertion directive, it says
@(posedge clk) tvalid // sampled value of tvalid ==1.
Then, @(negedge reset_n) ##1 // true. Then
@ next(posedge clk) !tvalid[*3];
As in any assertion, sampling is done in the Preponed Region of the clocking event, thus just before the event.
Show us the assertion directive. By itself, the sequence declaration does nothing. It’s a declaration, not a directive.
Ben systemverilog.us

Hi Ben,

I am only covering this sequence:

cov_sequence : cover sequence (
seq_reset_n_check(tvalid)
);

I think because of the sampling occurring in the preponed region, this statement is not doing what i expected it to do. Instead, I wrote an auxiliary function to aid me with this:

initial begin
	do begin
		@(posedge clk); @(negedge reset_n);
	end while (!valid);
	repeat (3) begin
		@(posedge clk);
		assert (valid == '0);
	end
end