In reply to ak180:
What you have is a sequence declaration.
@(posedge clk) tvalid ##1 @(negedge reset_n) 1’b1 ##1 @(posedge clk) !tvalid[*3];
Here you have 3 clocking events.
When that sequence is executed in an assertion directive, it says
@(posedge clk) tvalid // sampled value of tvalid ==1.
Then, @(negedge reset_n) ##1 // true. Then
@ next(posedge clk) !tvalid[*3];
As in any assertion, sampling is done in the Preponed Region of the clocking event, thus just before the event.
Show us the assertion directive. By itself, the sequence declaration does nothing. It’s a declaration, not a directive.
Ben systemverilog.us