Casting unpacked objects with width mismatch

SystemVerilog
1

Hi,
I have following code :


struct  { bit [7:0] a; shortint b;
       }a;

program myprog;
  int b;
  typedef logic[31:0] lgc_arr;
  lgc_arr x;
  initial begin
    b = int'(a);
    x = lgc_arr'(a);
  end
endprogram

“Typecast fails because the use of casting unpacked objects with width
mismatch: int’($unit::a)
Trying to cast a 24 bit object to a 32 bit object.This gives error message”

However, if I make struct packed, there is no error for both casts. I am not clear why casting only unpacked objects with width mismatch should give an error while packed objects do not give error while casting, even if there is width mismatch.

Also if bit stream types can be freely converted using explicit casts, what is the additional benefit streaming operators (pack/unpack) give?

rgs,
-sunil

2

In reply to puranik.sunil@tcs.com:

This is because of mixing strong and weak types in SystemVerilog. Integral packed types are weak types in SystemVerilog, they are silently truncated or extended when making assignments between differently sized types. A cast simply makes your intent explicit. Unpacked types have strong typing, and SystemVerilog requires the bit sizes to match.

The streaming operators don’t care about packed or unpacked. They have many features beyond just simple casting, like bit re-ordering. They also have more intelligent ways of dealing with dynamically sized arrays.

3

In reply to dave_59:

Thank you Dave for the explanation.
rgs,
-sunil