In reply to puranik.sunil@tcs.com:
This is because of mixing strong and weak types in SystemVerilog. Integral packed types are weak types in SystemVerilog, they are silently truncated or extended when making assignments between differently sized types. A cast simply makes your intent explicit. Unpacked types have strong typing, and SystemVerilog requires the bit sizes to match.
The streaming operators don’t care about packed or unpacked. They have many features beyond just simple casting, like bit re-ordering. They also have more intelligent ways of dealing with dynamically sized arrays.