Can SV queue based model be used for both synchronous and asynchronous fifo verification?

SystemVerilog
,
1

Can this code be used to verify both, synchronous and asynchronous FIFOs? I would instantiate it inside a scoreboard.

typedef longint int64;

class sync_fifo#(type T = int64);
    T sync_fifo[$];
    int fifo_size;

    function new(int size = 10);
        fifo_size = size;
    endfunction

    function void write(T data);
        if(sync_fifo.size() <= fifo_size) begin 
            sync_fifo.push_front(data);
            fifo_size++;
        end
        else begin
            $error("Writing full fifo!");
        end
    endfunction
    
    function T read();
        if(sync_fifo.size != 0) begin
            fifo_size--;
            return sync_fifo.pop_back();
        end    
        else begin
            $error("Reading empty fifo!");
            return 0;
        end
    endfunction

endclass;
2

In reply to Pooja Pathak:

That code would be problematic for a synchronous fifo if there was a simultaneous read and write on the same clock cycle and the fifo was empty or full. You would have a race condition with the read and write operations on whether or not they generate an error.

3

In reply to dave_59:

Any suggestions on how to fix it?

In a real FIFO if read and write happen at the same clock on an empty fifo, isn’t it an issue anyway? The write I imagine takes at least a cycle to complete, right?

4

In reply to Pooja Pathak:

But your write() method is a function consuming no time. If the queue is empty, the write() executes first, followed by the read(), the read succeeds. If the read()_ executes before the write() it fails. So you need to delay the push_front() by putting it inside a fork/join_none