In reply to dave_59:
Any suggestions on how to fix it?
In a real FIFO if read and write happen at the same clock on an empty fifo, isn’t it an issue anyway? The write I imagine takes at least a cycle to complete, right?
In reply to dave_59:
Any suggestions on how to fix it?
In a real FIFO if read and write happen at the same clock on an empty fifo, isn’t it an issue anyway? The write I imagine takes at least a cycle to complete, right?