Can SDF file cause incorrect driving of wires/ports?

SystemVerilog
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1

Let’s say these are bidirectional ports. In netlist the connection is,
IO1 ↔ IO2_a ↔ IO3_a
IO2_a ↔ IO3_b

Note: IO2_a branched out to IO3_a and IO3_b.

But in the SDF,
INTERCONNECT IO3_a IO3_b (…)
INTERCONNECT IO3_b IO3_a (…)

Note: IO3_a and IO3_b are driving each other according to the SDF file.

If IO1 is a toggling clock, while IO3_a is Hi-Z, can this cause IO3_b to become Hi-Z because of the SDF interconnect?

Regards,
Reuben