Calling function inside seq body

SystemVerilog
,
1

Hi,

Im trying to compile my code where I call write function inside seq body and Im getting the following error:

Error-[XMRE] Cross-module reference resolution error
testbench.sv, 15
  Error found while trying to resolve cross-module reference.
  token 'seq_item'.  Originating package '$unit'.
  Source info: seq_item.address = address;
  


Error-[XMRE] Cross-module reference resolution error
testbench.sv, 16
  Error found while trying to resolve cross-module reference.
  token 'seq_item'.  Originating package '$unit'.
  Source info: seq_item.data_bytes = new[4];
  


Error-[XMRE] Cross-module reference resolution error
testbench.sv, 17
  Error found while trying to resolve cross-module reference.
  token 'seq_item'.  Originating package '$unit'.
  Source info: seq_item.data_bytes = data_bytes;
  


Error-[XMRE] Cross-module reference resolution error
testbench.sv, 18
  Error found while trying to resolve cross-module reference.
  token 'seq_item'.  Originating package '$unit'.
  Source info: seq_item.byte_enable = new[4];
  


Error-[XMRE] Cross-module reference resolution error
testbench.sv, 19
  Error found while trying to resolve cross-module reference.
  token 'seq_item'.  Originating package '$unit'.
  Source info: seq_item.byte_enable = 4'hf;
  


Error-[XMRE] Cross-module reference resolution error
testbench.sv, 20
  Error found while trying to resolve cross-module reference.
  token 'seq_item'.  Originating package '$unit'.
  Source info: foreach (seq_item.data_bytes [i] ) begin
  seq_item.data_bytes[i] = address[(8 * i)+:0];
  seq_item.byte_enable[i] = data_bytes[(8 * i)+:0];
  end
  


Error-[XMRE] Cross-module reference resolution error
testbench.sv, 21
  Error found while trying to resolve cross-module reference.
  token 'seq_item'.  Originating package '$unit'.
  Source info: seq_item.data_bytes[i] = address[(8 * i)+:0];
  


Error-[XMRE] Cross-module reference resolution error
testbench.sv, 22
  Error found while trying to resolve cross-module reference.
  token 'seq_item'.  Originating package '$unit'.
  Source info: seq_item.byte_enable[i] = data_bytes[(8 * i)+:0];

This is the code that has been compiled:

class c1;
  rand byte unsigned byte_data[];
  rand longint unsigned address;
  rand bit byte_enable[];
  
  virtual task body();
    c1 seq_item;
    seq_item =new();
    $display("Write Done ...");
	    //Call write function
    write(32'h0100_0814,32'h01);  
  endtask :body
  
  function void write(int address, int data_bytes);
     seq_item.address                   = address;
     seq_item.data_bytes                = new[4];
     seq_item.data_bytes                = data_bytes;
     seq_item.byte_enable               = new[4];
     seq_item.byte_enable               = 4'hF;
     foreach(seq_item.data_bytes[i]) begin
       seq_item.data_bytes[i] = address[8*i +:0];
       seq_item.byte_enable[i] = data_bytes[8*i +:0];
       end
   endfunction	  
endclass : c1

I am stucked and not sure why I get this error. I have checked for the typos, semicolon/brackets checks and any mismatches errors but I cant seem to find any. Is there anything wrong in the code?

2

In reply to basilleaf:

Please post a small example that is executable. The above code doesn’t have definitions of avmm_seq_item.

3

In reply to rag123:
Below is an executabale code:

class c1;
  rand byte unsigned byte_data[];
  rand longint unsigned address;
  rand bit byte_enable[];
 
  virtual task body();
    c1 seq_item;
    seq_item =new();
    $display("Write Done ...");
	    //Call write function
    write(32'h0100_0814,32'h01);  
  endtask :body
 
  function void write(int address, int data_bytes);
     seq_item.address                   = address;
     seq_item.data_bytes                = new[4];
     seq_item.data_bytes                = data_bytes;
     seq_item.byte_enable               = new[4];
     seq_item.byte_enable               = 4'hF;
     foreach(seq_item.data_bytes[i]) begin
       seq_item.data_bytes[i] = address[8*i +:0];
       seq_item.byte_enable[i] = data_bytes[8*i +:0];
       end
   endfunction	  
endclass : c1
4

In reply to basilleaf:

why do you declare c1 class object in c1 class ?

5

In reply to kitanisi:

That is how we declare class object right? Is it wrong? Or i should declared it inside a module?

6

In error code


class c1;
  rand byte unsigned byte_data[];
  rand longint unsigned address;
  rand bit byte_enable[];
 
  virtual task body();
    c1 seq_item;
    seq_item =new();
    $display("Write Done ...");
	    //Call write function
    write(32'h0100_0814,32'h01);  
  endtask :body
 
  function void write(int address, int data_bytes);
     avmm_seq_item.address                   = address;  // <- where you declare avmm_seq_item in class c1?
     avmm_seq_item.data_bytes                = new[4]; // <- where you declare avmm_seq_item ?
     avmm_seq_item.data_bytes                = data_bytes; // <- where you declare avmm_seq_item ?
     avmm_seq_item.byte_enable               = new[4]; // <- where you declare avmm_seq_item ?
     avmm_seq_item.byte_enable               = 4'hF; // <- where you declare avmm_seq_item ?
     foreach(seq_item.data_bytes[i]) begin
       seq_item.data_bytes[i] = address[8*i +:0];
       seq_item.byte_enable[i] = data_bytes[8*i +:0];
       end
   endfunction	  
endclass : c1

And if you use recursive class, it’s good to read a URL below.
https://verificationacademy.com/forums/systemverilog/class-recursion-due-parameterization

7

In reply to kitanisi:

It is not avmm_seq_item… just seq_item. I made a typo there when testing the code in EDA playground.

class c1;
  rand byte unsigned byte_data[];
  rand longint unsigned address;
  rand bit byte_enable[];
 
  virtual task body();
    c1 seq_item;
    seq_item =new();
    $display("Write Done ...");
	    //Call write function
    write(32'h0100_0814,32'h01);  
  endtask :body
 
  function void write(int address, int data_bytes);
     seq_item.address                   = address;
     seq_item.data_bytes                = new[4];
     seq_item.data_bytes                = data_bytes;
     seq_item.byte_enable               = new[4];
     seq_item.byte_enable               = 4'hF;
     foreach(seq_item.data_bytes[i]) begin
       seq_item.data_bytes[i] = address[8*i +:0];
       seq_item.byte_enable[i] = data_bytes[8*i +:0];
       end
   endfunction	  
endclass : c1

I still get the same error.

8

In reply to basilleaf:

You have declared seq_item local to the task body(), it is not visible to the write() method. Either pass it through an argument, or declare it as a shared class member, not inside the method.

As this code looks suspiciously like a uvm_sequence, there is already a sequence_item declared with the name ‘req’, so you do not need to declare a separate variable.

9

In reply to dave_59:

Thank you Dave. Understood.