Calling function inside seq body

SystemVerilog
,
6

In error code


class c1;
  rand byte unsigned byte_data[];
  rand longint unsigned address;
  rand bit byte_enable[];
 
  virtual task body();
    c1 seq_item;
    seq_item =new();
    $display("Write Done ...");
	    //Call write function
    write(32'h0100_0814,32'h01);  
  endtask :body
 
  function void write(int address, int data_bytes);
     avmm_seq_item.address                   = address;  // <- where you declare avmm_seq_item in class c1?
     avmm_seq_item.data_bytes                = new[4]; // <- where you declare avmm_seq_item ?
     avmm_seq_item.data_bytes                = data_bytes; // <- where you declare avmm_seq_item ?
     avmm_seq_item.byte_enable               = new[4]; // <- where you declare avmm_seq_item ?
     avmm_seq_item.byte_enable               = 4'hF; // <- where you declare avmm_seq_item ?
     foreach(seq_item.data_bytes[i]) begin
       seq_item.data_bytes[i] = address[8*i +:0];
       seq_item.byte_enable[i] = data_bytes[8*i +:0];
       end
   endfunction	  
endclass : c1

And if you use recursive class, it’s good to read a URL below.
https://verificationacademy.com/forums/systemverilog/class-recursion-due-parameterization