Can you declare a bind statement inside a SystemVerilog interface?
If I have a module with assertions can I used the bind statement within the interface file?
In reply to GChan:
Creating a new instance using the bind construct is subject to the same semantics had you explicitly created the instance inside that other instance. Interfaces may contain instances of other interfaces, but not modules. Modules may may contain instances of other modules or interfaces.
A bind construct itself may be located in an interface or module.
In reply to dave_59:
You can also bind a SystemVerilog checker to an interface or a module.
From my SVA Handbook 4th Edition, 2016 ISBN 978-1518681448 I demonstrate that feature. See image below.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115