Behavior

SystemVerilog
1

Hi all


1. @(posedge clk); // with;
   begin 
      a<=A;
      b<=B;
   end
2  @(posedge clk)   // no;
   begin
     a<=A;
     b<=B;
   end

What is the difference between case1 and case2 in system verilog? it seems that the waveform of two case are same/
Thanks a lot!!

2

In reply to peter:
Take a look at the syntax:


// A.6.2 Procedural blocks and assignments
initial_construct ::= initial statement_or_null
always_construct ::= always_keyword statement
always_keyword ::= always | always_comb | always_latch | always_ff
final_construct ::= final function_statement

A.6.4 Statements
statement_or_null ::=
  statement
  | { attribute_instance } ;
statement ::= [ block_identifier : ] { attribute_instance } statement_item
statement_item ::=
  ... procedural_timing_control_statement 
  | ... see 1800'2017 

procedural_timing_control_statement ::=
  procedural_timing_control statement_or_null

procedural_timing_control ::=
  delay_control
  | event_control
  | cycle_delay

event_control ::=
@ hierarchical_event_identifier
| @ ( event_expression )
| @*
| @ (*)
| @ ps_or_hierarchical_sequence_identifier

// Thus, 
module m; 
    bit a, b, c, d, clk;    
    always begin  // blocking statement 
        @(posedge clk); 
// LEGAL. The event control @(posedge clk) is followed by the statement ";"
/* statement_or_null ::=
statement
| { attribute_instance } ;  */
        a <= b;
    end 

    always @(posedge clk)  c <= !c; 
// LEGAL because 
/* statement_item ::=
   procedural_timing_control_statement 
   and that is 
    procedural_timing_control_statement ::=
      procedural_timing_control statement_or_null 
       <--------------------->   <---------->
        @(posedge clk)           c <= !c */
    
    always @(posedge clk);  c <= !c;  // line 11 
    // (11): near "<=": syntax error, unexpected <=.
   /*      procedural_timing_control statement_or_null 
          <--------------------->          <---------->
            @(posedge clk)                    ;   */

// The "c <= !c;"  by itself is illegal in a module 

endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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3

In reply to ben@SystemVerilog.us:

so, two case are LEGAL. but , they are same?

4

In reply to peter:

Yes, the same

 

always begin  // blocking statement 
        @(posedge clk); // the ";" does nothing 
    // it's an empty statement 
        a <= b;
    end 
 
    always @(posedge clk)  c <= !c;
5

In reply to ben@SystemVerilog.us:

Not always the same. Your code needs more context.

The BNF syntax for any procedural statement is essentially

statement_item := 
        {procedural_timing_control} statement;

This means you can have 0 or more timing controls in front of any statement. In your example,
@(posedge clk) is a timing control and the
begin/end block is the statement.

If your example were inside a fork/join, there would be a behavioral difference because the case 1 is two statements; and case 2 is one statement.

fork
@(posedge Clk);
begin
a<=A;
b<=B;
end
join
In this case, the 2 statements are started in parallel - The assignments to a and b would not wait for the posedge of clk.

Please see this post about why complete examples are needed to get correct answers.