Basic of `define Macros

SystemVerilog
, ,
1

Hi guys,

**********************file_1.sv****************************
// i want to use `define macro 

`define REG\
int int1=1;\
string str1="Hi";

*********************file_2.sv****************************
module tb;
  
  `REG

  initial begin
  $display("str1=%s int1=$d",str1,int1);
  end

endmodule

My questions are :

  1. can i use int and string keyword in macro’s ?
  2. if no, then is there any alternative way ?, if yes, then it is showing error while compilation.

Regards,
Alok

2

In reply to Alok_Mandal:

A `define is processed as a simple substitution. There may be some subtle coding requirements for some use cases, but for the most part it is straight forward.

If you are getting an error, you will have to post a complete example that demonstrates your error and the error message(s) you are getting.

Since `defines are limited to the scope which they are defined in, did you include file_1.sv in file_2.sv?

3

In reply to cgales:
i forget to include file_1.sv inside file_2.sv

Thanks,

*******************file_1.sv*************************
// modified `define macro 

1.`define REG\
2. int int1=6;\
3. string str1="Hi";\
4.
5. int int2=8;\ 
6. string str2= "Guys";
*****************************************************

*********************file_2.sv****************************
`include "file_1.sv"

module tb;
  
  `REG

  initial begin
  $display("str1=%s int1=%d str2=%s int2=%d",str1,int1,str2,int2);
  end

endmodule
***********************************************************

line no. 4 is intentionally left blank, when i include this file and run file_2.sv, it pop up ERROR, but if statement written in line no. 5 is shift to line no. 4 and line no. 5 is left blank then it does not pop up error.

So my questions are :

  1. is there any way to overcome this blank line problem ?(don’t tell me to shift the code up, i intentionally want to keep first sets of int1 , str1 to separate from second set of int2 ,str2).
  2. when blank line is at #4 then it doesn’t work but when it is on #5 it works, why ? (is there any rule which i am missing ?).

regards,
Alok