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  • In AXI3 VIP, getting assertion error as well default transaction type is being picked up with values zeroes being displayed.

In AXI3 VIP, getting assertion error as well default transaction type is being picked up with values zeroes being displayed.

SystemVerilog 5105
assertion errors 3 Failing testcases 1 no values displayed 1
saikanthan7798
saikanthan7798
Forum Access
12 posts
February 11, 2021 at 4:20 pm

In this code, whatever the testname being given, it is printing only WR's values and if testname is changed, no values are being generated.

PLease find the code below

https://www.edaplayground.com/x/Q8SR

The following data being shown below was from QuestaSim.

-->Giving Test name as WRITE and Read fields are being displayed with no values
Let's say testname=TEST_10_WR_TX"
o/P:
** Error: Assertion error.
# Time: 0 ns Scope: axi_header_svh_unit.gen.run File: gen.sv Line: 10
# ** Error: Assertion error.
********Printing read fields************
# read_id=0
# read_addr=00000000
# read_data='{}
# read_length=0
# read_size=0
# read_burst=00000000
# bfm::read_addr
# bfm::read_data
# ********Printing read fields************
--> GIving READ as test name
********Printing read fields************
# read_id=e
# read_addr=ed12865d
# read_data='{2582994940, 2846503663, 3186666722, 3981055222}
# read_length=3
# read_size=1
# read_burst=00000002
# bfm::read_addr
# bfm::read_data
Read testcase is getting correct values
----> Giving WR_RD as test name = TEST_10_RD_TX
** Error: Assertion error.
# Time: 0 ns Scope: axi_header_svh_unit.gen.run File: gen.sv Line: 24
# inside mon
# inside cov
# ********Printing read fields************
# read_id=0
# read_addr=00000000
# read_data='{}
# read_length=0
# read_size=0
# read_burst=00000000
# bfm::read_addr
# bfm::read_data

How to get rid of those assertion errors and get the testcases being passed.

Replies

Log In to Reply
cgales
cgales
Forum Moderator
1606 posts
February 12, 2021 at 4:00 am

In reply to saikanthan7798:

You should never use an assert statement with a call to randomize(). Instead, you should use the return code to determine if the call was successful:

case(cfg_axi::testname)
  "TEST_10_WR_TX":begin
    for(int i=0;i<9;i=i+1) begin
      tx=new();
      if (!(tx.randomize() with {tx.tx_type == WRITE;}))
        $display("Randomization failed!");
      else
        cfg_axi::gen2bfm.put(tx);
    end
  end

In this case, you would receive the error message that the call to randomize() failed.

You would then focus on the error message:
# axi_gen:: inside gen
# gen.sv(10): randomize() failed due to conflicts between the following constraints:
# gen.sv(10): (tx_type == WRITE);
# Where:
# tx_type = READ /* non-random */

In the axi_tx class, tx_type is not declared as 'rand', hence it can't be randomized.

saikanthan7798
saikanthan7798
Forum Access
12 posts
February 12, 2021 at 9:07 am

In reply to cgales:

Hi cgales,

THank you for responding. It is working now. But TEST_WR_RD_2000_TX" is not getting the desired outcome. WHy is it so??

Where can I get clarity and in-depth knowledge about SVA?

regardsm,
Krishna.

cgales
cgales
Forum Moderator
1606 posts
February 12, 2021 at 9:27 am

In reply to saikanthan7798:

You will need to update your environment on EDA Playground so we can see the issues you are facing.

Regarding assertions, there are a lot of resources available on the Internet.

Solution

Solution

saikanthan7798
saikanthan7798
Forum Access
12 posts
February 16, 2021 at 5:44 pm

Hi,

Even though I have declared pif, it is showing as undefined variable. Not sure what's the issue.
//declaring clk & reset
reg clk,rst;
//logic to get user input
initial begin
$value$plusargs("testname=%s",cfg_axi::testname);
cfg_axi::vif=pif;
end

//instantiate interface
intf pif(clk,rst);
//testbench instantiate
tb tb();

Error

** Error: ** while parsing file included at axi_header.svh(11)
# ** at top.sv(56): (vlog-2730) Undefined variable: 'pif'.
# End time: 07:03:48 on Feb 17,2021, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
# ** Error: /home/tools/mentor/questasim/linux/vlog failed.
# Error in macro ./run.do line 1
# /home/tools/mentor/questasim/linux/vlog failed.
# while executing
# "vlog axi_header.svh"

cgales
cgales
Forum Moderator
1606 posts
February 17, 2021 at 3:28 am

In reply to saikanthan7798:

At the time you are referencing 'pif', it hasn't been declared. You should move your initial block to the end of your top module, after all of your module/interface instantiations.

saikanthan7798
saikanthan7798
Forum Access
12 posts
February 19, 2021 at 9:27 pm

In reply to cgales:

Hi cgales,

I couldn't see any transaction being performed in the following code. Please advise if there're any changes.

https://www.edaplayground.com/x/Q8SR

thanks,
Krishna

cgales
cgales
Forum Moderator
1606 posts
February 20, 2021 at 5:10 am

In reply to saikanthan7798:

You have a race condition where you are starting your test prior to setting the testname, hence the generator is creating nothing.

You should be sequencing getting/setting the test name and creating/running your environment at the top level. Don't use an intermediate tb to start the environment.

saikanthan7798
saikanthan7798
Forum Access
12 posts
February 21, 2021 at 8:24 pm

In reply to cgales:

After seqencing at the top level, I could see 10 read transactions being generated but only 2 write transactions .

https://www.edaplayground.com/x/Q8SR

cgales
cgales
Forum Moderator
1606 posts
February 22, 2021 at 4:23 am

In reply to saikanthan7798:

The link that you posted doesn't do anything similar to your question. If you want assistance, you need to ensure that you are posting correct information.

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