Assign statement

SystemVerilog
,
1 
module tb;
  wire [3:0] a;

  assign a = 2;
  assign #5 a = 3;

  always @(a) 
    $monitor($time, a);
endmodule

The above code is giving a result ‘x’ for net ‘a’ at 5ns. Can someone explain why I am getting ‘x’, while system verilog LRM specifies “Nets can be driven by multiple continuous assignments” in 10.3.2. Each of the continuous assignments when used alone are giving expected results i.e., a = 2 at 0ns and a = 3 at 5ns.

2

In reply to Naveenkb:
Try displaying a in binary.

$monitor("%t %b",$time, a);
3

Thank you Dave. The result is 001x at 5ns, which are the resolved values for each wire in the net as I understand(correct me if I am wrong). But why there was no value assigned at time 0?