Assertion Property : Non consecutive repetition operator

Hello,
I am using a non-consecutive repetition operator as below for which the limit is coming from a a register field bit[3:0]

property ready_valid_check(clk,reset,logic ready,logic valid,int delay); 
  @(posedge clk) disable iff(!reset)
  !ready |=> valid [=0:delay]  ##1 ready
endproperty : ready_valid_check 

property_1 : assert property(ready_valid_check(clk_i,rst_n,top_tb.dut.ready_i,top_tb.dut.valid_o,int'(top_tb.dut.reg_block.cfg_reg.delay[3:0]))) 
  else  $error("Assertion Failed for property_1 ");

But I was getting an elaboration error

The use of a non-constant expression is not allowed in properties, sequences
and assertions for cases such as delay and repetition ranges.
Please replace the offending expression by an elaboration-time constant.

How can we overcome this ? Any suggestions ?
Thanks in advance.

Regards,
Shinto

In reply to jshintok:

See Variable Delay for SystemVerilog Assertion | Verification Academy