Assertion fail

SystemVerilog
,
1 
module test;
bit clk;
bit rst;
bit bus_master;
//  string master="master";

  
always clk =#5 !clk;

  `define bus_assertion_macro(STR) \
  property bus_``STR``_sig_ckh_p; \
    @(posedge clk) disable_iff(rst) (1 |-> $changed(bus_``STR));\
  endproperty
  
  `bus_assertion_macro(master)
  bus_master_ckh: assert property(bus_master_sig_ckh_p);
    
  
 initial
   begin
     rst = 1;
     #20
     rst =0;
     @(negedge clk); 
     bus_master=1;
     @(negedge clk); 
     bus_master=0;     
   end
  
    
endmodule

///***Error is
Error-[SE] Syntax error
Following verilog source has syntax error :
“testbench.sv”, 15 (expanding macro): token is ‘(’
`bus_assertion_macro(master)
^

#0, bus_assertion_macro(STR=master) : “testbench.sv”:12
full expansion of macro (bus_assertion_macro), error at line 2
property bus_master_sig_ckh_p;
=> @(posedge clk) disable_iff(rst) (1 |-> $changed(bus_master));
endproperty
1 error
CPU time: .068 seconds to compile

2

In reply to deep1234:

There is no _ between disable and iff.

3 
`define bus_assertion_macro(index) \
property bus_sig_ckh_p[index]; \
@(posedge clk) disable iff (rst) (1 |-> bus_master[index]);\
endproperty
  
generate
for (index=0; index < 4; index++) 
begin
`bus_assertion_macro(index) 
bus_master_ckh[index]: assert property(bus_sig_ckh_p[index]);
end
endgenerate

My application is to generate multiple assertions with micros (that’s possible with above code) but I want to trigger assertions, so I use generate-loop to call multiple assertions, but it always takes input as a string “index”. Assertion “`bus_assertion_macro(index)”; index replace with index string, but I want to replace with values(0,1,2,3) in generate loop.

4

In reply to deep1234:

Welcome to the Verification Academy. You really should be asking this as a new question. And please use code tags when posting your code.

Macros in your source code get processed before any SystemVerilog gets parsed. But there’s no need to use a macro here

property bus_sig_ckh_p(index); 
@(posedge clk) disable iff (rst) (1 |-> bus_master[index]);
endproperty
 
generate
for (index=0; index < 4; index++) 
  begin : loop
    bus_master_ckh: assert property(bus_sig_ckh_p(index));
  end
endgenerate

This generate the assertions loop[0] bus_master_ckh, loop[1] bus_master_ckh, loop[2] bus_master_ckh, loop[3] bus_master_ckh

5

Thanks for the quick reply. But this is only my snippet example code, but I need to write an assertion where hierarchy path also used so I need to replace those hierarchy instances with macros as well.
I agree with your answer. But any work-around that where we can use macros and functionality of (generate-loop or any other).