I have a design that has two inputs and one output. So, there can be glitches on the inputs. On my first input, I have two glitches with some delay in between them. I have to write an assertion to check if I have any glitch on the second input which falls between the two glitches on another input.
In reply to Vikram Gupta:
Not all assertions are best handled in SVA. However, keep in mind the meaning of an assertion:
Assertion: A statement or directive that a given property is required to hold. Assertions allow for automated checking that the specified property is true, and can generate automatic error messages if the property is not true. An assertion is a “statement about a design’s intended behavior” (From Assertion-Based Design, Foster).
SVA is just a way or notation to express an assertion, but SVA has many restrictions.
In my paper SystemVerilog Assertions Alternative for Complex Assertions | Verification Academy I explain SVA Alternative for Complex Assertions.
Below is a model that I believe fits your needs, but feel free to modify it to meet your requirements. It uses tasks. A testbench is also provided.
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
timeunit 1ns; timeprecision 100ps;
bit clk, a, b, go;
event e, e0;
default clocking @(posedge clk);
endclocking
initial forever #10 clk=!clk;
// I have two glitches with some delay in between them.
// I have to write an assertion to check if I have any glitch
// on the second input which falls between the two glitches on another input.
task automatic glitch2();
@(posedge a) fork
begin : s1
@(posedge b) `uvm_error("MYERR", "b in between 2 a")
-> e;
disable glitch2;
end : s1
begin :s2
@(posedge a) `uvm_info("TEST", "no glitch in tween 2 a", UVM_LOW)
->e0;
disable glitch2;
end :s2
join_any
endtask
always @(posedge clk) if (go) glitch2(); // the Assertion
initial begin
bit va, vb, vgo;
repeat(200) begin
@(posedge clk);
if (!randomize(va, vb, vgo) with
{ va dist {1'b1:=1, 1'b0:=3};
vb dist {1'b1:=1, 1'b0:=8};
vgo dist {1'b1:=1, 1'b0:=10};
}) `uvm_error("MYERR", "This is a randomize error")
a <= va;
b <= vb;
go <= vgo;
end
$stop;
end
endmodule
// simulation
# UVM_ERROR .\twosigs.sv(18) @ 2100: reporter [MYERR] b in between 2 a
# UVM_ERROR .\twosigs.sv(18) @ 4500: reporter [MYERR] b in between 2 a
# UVM_ERROR .\twosigs.sv(18) @ 13100: reporter [MYERR] b in between 2 a
# UVM_INFO .\twosigs.sv(24) @ 17100: reporter [TEST] no glitch in tween 2 a
# UVM_ERROR .\twosigs.sv(18) @ 18100: reporter [MYERR] b in between 2 a
# UVM_INFO .\twosigs.sv(24) @ 22100: reporter [TEST] no glitch in tween 2 a
# UVM_INFO .\twosigs.sv(24) @ 24700: reporter [TEST] no glitch in tween 2 a
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
In reply to ben@SystemVerilog.us:
Hi Ben,
Is it meaningful to think above assertion requirement in this way:
- Iinput first is in1 and another input is in2. Calculating at what time glitches are there in in1. Since there are already two glitches in in1, so they are happening at t1 and t2.
sequence s1;
($rose(in1), t1 = $time);
endsequence
Similarly for in1.
sequence s2;
($rose(in1), t2 = $time);
endsequence
For glitch if any at in2.
sequence s3;
($rose(in2), t3 = $time) |=> (t3>t1) && (t3<t2);
endsequence
property p1;
@(posedge clk)
s1 |=> s2 |=> s3;
endproperty
assert property (p1);
Kindly let me know can we look at the problem in this way. The syntax may be wrong here but trying to know the issue in this way?. Three sequences and one property…
In reply to sunils:
- Need to define what a “glitch” is. The requirements are not clear.
- I understood the word “glitch” to mean a spike, and is thus asynchronous to any clock.
The statement was Detect a glitch between two glitches - If the requirements were Detect a synchronous pulse two clocked signals, then that requirement can be tranlated to:
If rose(a) then no “b” until next rose(a), or in SVA
@(posedge clk) rose(a) |-> !b[*1:] ##1 $rose(a);
Aside for syntax errors, the property will not do the job.
property p1;
@(posedge clk) s1 |=> s2 |=> s3;
// You expect s2 to start at the next clocking event, but it can start later.
// In addition, the local variables for sequence and s2 used to store the time are local to the sequence and not visible in s3
endproperty
// You probably meant to say
property p_sync; // WILL NOT WORK BECAUSE t1a and t2 CANNOT see t3b because of the "or"
realtime t1a, t2a, t3b; // assuming a synchonous system
@(posedge clk) ($rose(in1), t1a = $realtime, t3b=$realtime) |=>
(($rose(in1}[->1], t2a=$realtime) or
($rose(in2}[->1], t3b=$realtime)) ##0 (t3b <t2b); // will NOT WORK
endproperty
//BTW, you have too many implication operators.
// If you meant an asyn system, tehn you probably meant
property p_async; // WILL NOT WORK BECAUSE t1a and t2 CANNOT see t3b because of the "or"
realtime t1a, t2a, t3b; // assuming a synchonous system
@($rose(in1) (1,t1a = $realtime, t3b=$realtime) |=>
((@$rose(in1} (1,t2a=$realtime) or
(@$rose(in2} (1,t3b=$realtime)) ##0 (t3b <t2b); // will NOT WORK
endproperty
Go back to the requirements, is this a synchronous or asynchronous system?
The above assertion can be made to work through some static task to store those local variables, but that is very messy and is subject to errors because you need to clean up those variables. Anyway, I like my solution better, but am open to other ideas.
Thanks for your inputs.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115