Assertion to Detect a glitch between two glitches

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Hi Ben,

Is it meaningful to think above assertion requirement in this way:

  1. Iinput first is in1 and another input is in2. Calculating at what time glitches are there in in1. Since there are already two glitches in in1, so they are happening at t1 and t2.
sequence s1;
($rose(in1), t1 = $time);
endsequence

Similarly for in1.
sequence s2;
($rose(in1), t2 = $time);
endsequence

For glitch if any at in2.

sequence s3;
($rose(in2), t3 = $time) |=> (t3>t1) && (t3<t2);
endsequence

property p1;
@(posedge clk)
s1 |=> s2 |=> s3;
endproperty

assert property (p1);

Kindly let me know can we look at the problem in this way. The syntax may be wrong here but trying to know the issue in this way?. Three sequences and one property…