Assertion Delay from Register

SystemVerilog
,
1

Hello,

$rose(digi_en & init_trigger) |-> ##[0:RISE_DLY] (digi == 1) ##[1:FALL_DLY] (digi == 0) ;
Can RISE_DLY and FALL_DELAY can come from a Programmable Register for Assertions.

Thanks
JeffD

2

In reply to dvuvmsv:

See the links in this discussion.