Assertion check on delay using $time

SystemVerilog
, ,
1

I want to do an assertion check where signal B must high 5000s after signal A is high.

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I tried this code but I got an error regarding “multi-clock overlapping”


property Check_RXENA;
realtime start;
@(posedge pll_clk0)
if((clksel == 0) && (txsel ==0))
(@(posedge pll_clk0) (1,start=$realtime) ##0 @(posedge rx_ena) $realtime-start==5000);
endproperty

May I know if there is other suitable approach on how to do this?

2

In reply to lisa.lalice:
I would have written your assertion this way.


module top;
  timeunit 1ns;  timeprecision 100ps;    
  bit pll_clk0, clksel, txsel, rx_ena;

  property Check_RXENA;
    realtime start;
    @(posedge pll_clk0)
      (clksel == 0 && txsel ==0, start=$realtime) |-> 
                         @(posedge rx_ena) $realtime-start==5000;
  endproperty
  ap: assert property(Check_RXENA);    
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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