hi,
property p1;
@(posedge PCLK) $fell(LINTX);
endproperty
not working?
LINTX stays for 4 clocks of PCLK.
In wave it is seen the marker are red where LINTX is high but empty in LINTX going low.
please suggest
In reply to ramandeepk:
It would help if you
- Used code tags in your posts to make them more readable (I added them for you)
- Used unique question titles that summarized the issue.
- Showed a more complete example.
In reply to dave_59:
// or browse Examples
module testbench;
logic clk =1’b1;
logic test =0;
always
#2 clk = ~clk;
always @(posedge clk)
#4 test = ~test;
initial
begin
$dumpfile("dump.vcd"); $dumpvars;
#100 $finish();
end
property p1;
@(posedge clk) (!test);
endproperty
assert property(p1);
endmodule
result:
Compiler version J-2014.12-SP1-1; Runtime version J-2014.12-SP1-1; Mar 6 05:53 2019
“testbench.sv”, 26: testbench.unnamed$$_1: started at 8ns failed at 8ns
Offending ‘(!test)’
“testbench.sv”, 26: testbench.unnamed$$_1: started at 16ns failed at 16ns
Offending ‘(!test)’
“testbench.sv”, 26: testbench.unnamed$$_1: started at 24ns failed at 24ns
Offending ‘(!test)’
“testbench.sv”, 26: testbench.unnamed$$_1: started at 32ns failed at 32ns
In reply to ramandeepk:
not working?
LINTX stays for 4 clocks of PCLK.
What you are stating above is an incomplete requirement. Keep in mind that assertions reflect the requirements. A requirement that a signal is HIGH for 4 cycles is meaningless because its context is ambiguous; Under what conditions does it go HIGH? Think about it, what if I say the traffic light goes red for 2 minutes. Is that after is it amber? during maintenance?
From my SVA Handbook 4th Edition
Requirements are typically defined in a document. The “design requirements” should be free of implementation. The following subsections address types of requirements that can be supported by SVA to clarify the intent.
6.3.1 Cause and effect class of requirements
Many system-level requirements can usually be represented as cause-effect relationships. In SystemVerilog, the “cause” is called the antecedent, and the “effect” is called the consequent. For example:
Requirement: If the design is subjected to a command to fire the pyro X then within 5 cycles the pyro X relay shall be activated.
SVA property definition:
property pFirePyro; // use of the clock is important only if it adds significance
@ (posedge clk) xaction.Fire_PyroX_CMD==FIRE |->
## [1:5] pyro_sub.PyroX_relay==ACTIVATED;
Before writing a complex assertion, I suggest that you write the requirements in English.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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