Assert is failing before I do assertoff at time 0 in initial block

SystemVerilog
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1

I have an assertion thats failing at time 0. I’m trying to disabled it by assertoff in the test top initial block. But the assert is failing at time 0 just before I do assertoff. Is there a way to overcome this? I dont have any delayes before assert off.

2

In reply to ravitejavoora:

Most simulators provide a command-line option to disable assertions. Refer to your tool documentation or contact your vendor support team for additional assistance.

3

In reply to cgales:


property p; .@(posedge clk).. .; endproperty 
initial @(posedge clk) assert property(always p);

// if immediate assertion 
@(posedge clk) begin 
  .... 
  assert($realtime>0 && expression);
end