Application of interface classes in System verilog

in LRM i found interface classes which has multiple inheritance properties but where we can use it.
i mean scenario in real world??.

This is a fairly advanced topic and most likely used by people writing class libraries, not test writers. Look at this thread for links for further reading.

I’ve written two blog posts, one on interface classes and one on faking multiple inheritance. You can find them here:

SystemVerilog 2012 Has Even More ‘Class’
Fake It 'til You Make It - Emulating Multiple Inheritance in SystemVerilog

These are based on some toy examples.

In reply to Tudor Timi:

Hi Timi,

The blog you have mentioned, In this top portion is not loading.

In reply to anilhr:

Seems to be working fine for me.