"always_ff" clearity

SystemVerilog
1

Hello,

always_ff @ (posedge clk, negedge rst_n)
     if (~rst_n)
       begin
        statements
     end

i have tried to understand the meaning of always_ff but couldn’t get it clearly. Please help me with the always_ff code. i am trying to debug my testcase and while tracing the drivers i found above code from RTL.

Thanks

2

In reply to chandnidodiya:

always_ff behaves exactly the same as always. It has a few more compile phase restrictions/checks for synthesizability.

3

For this, always_ff @ (posedge clk, negedge rst_n), “,” refers to “OR” or “AND” operation?

4

In reply to chandnidodiya:

OR. In fact you can use that instead of “,”.

always_ff @(posedge clk or negedge rst_n)
5

In reply to chandnidodiya:

You cannot AND events.

See 9.4.2.1 Event OR operator in the IEEE 1800-2017 LRM

6

In reply to dave_59:

Thank You.

7

In reply to sbellock:

Thank you.