Accessing hierachy via `define

SystemVerilog
,
1

I have module hierarchy as top.A[0].B.C , top.A[1].B.C , top.A[2].B.C

In the top module I have an array of instances for a .


module top ;

a A [2:0] () ;

endmodule

Now from an initial block in top module I would be accessing a function within instance ‘C’


  initial begin
 
    A[0].B.C.DISP();
    A[1].B.C.DISP();
    A[2].B.C.DISP();
  end

Now rather than writing it down each time , I want to use a compiler directive


`define S(i) A[i].B.C.DISP(); 

  initial begin
  
   for ( int x = 0 ; x < 3 ; x++ )
    begin
       `S(x)
    end

   end

Now this doesn’t work since it tries to access A.B.C.DISP() which is incorrect .

Any suggestions ?

2

In reply to Have_A_Doubt:

`define text macros get expanded before any SystemVerilog code gets parsed. See this discussion

3

In reply to dave_59:

An addition to the original question .

I actually wanted the behavior from within a class method , **is there a way to achieve the

same within a class method ?**

4

In reply to Have_A_Doubt:

How about showing a minimally complete example of what you want assuming there was only one instance of module A?

5

In reply to dave_59:



module top ;

 `define S(i) A[i].B.C.DISP(); 
  
 import uvm_pkg::*;
 import my_pkg::* ; // Will include my_test

a A [2:0] () ; // module a contains instance of module b ,
               // module b contains instance of module c .
 
 initial begin
   run_test("");
  end

endmodule

//  my_test would be there be in another path/folder which is included in my_pkg .
  class my_test extends uvm_test ;
  
   // Factory registration and Standard 3-line Constructor 

   task main_phase ( uvm_phase phase ) ;
 
   for ( int x = 0 ; x < 100 ; x++ )
    begin
       `S(x)
    end
     

   endtask