Write an assertion ,after the clk has arrived within 5 clk cycles write or read should not occur

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

In reply to SUNODH:
One of the main requirements is “at the initial stage of clk”.
That is not well defined, but it typically means during the forst “n” clock after boot.
Assuming n==10, you could use an initial statement with a loop for 10 clocking events.
There you can write a concurrent or an immidiate assertion.

Thank You Ben as per your instruction I used below logic it worked for me


  initial
    begin
    repeat(10)
      begin
        @(posedge clk)
        assert (!read && !write)
          $display ($time, " PASS:: write = %0d, read = %0d   |  @_Time = %0t\n", $sampled(write),$sampled(read),$time);
        else
          $fatal ($time, " FAIL:: write = %0d, read = %0d   |  @_Time = %0t\n", $sampled(write),$sampled(read),$time); 
      end
    end

But I like to use

not (!read && !write)

&

first_match (not_read_write)

and what I know is we can’t use them in an immediate assertion.
Are they any way we can check this assertion using the assert property?