Does SystemVerilog allow to collect coverage on Testbench code?

Coverage
1

Hello,
I have a question around robust verification approach.

Let’s assume I have a Testbench with an infrastructure in place to:

  • Collect code coverage on the DUT
  • Collect functional coverage to make sure all stimuli of interested were hit as desired (as per constrained-random definition) by Testbench

What I would like to add is the support to some sort of coverage in the TB code itself. Let’s assume for example I have a specialized checker called Checker_X in my TB which is supposed to check something through a task (or function) called TaskOrFunct_A. The expectation is that Checker_X :: TaskOrFunct_A() gets called by the TB at runtime, at some point in time, to check for example some register values of the DUT.

I would like to know if SystemVerilog language allows to collect something similar to code/functional coverage on Checker_X :: TaskOrFunct_A(). In other words: after I run a regression with 10,000 tests in it, was Checker_X :: TaskOrFunct_A() called for each of those tests? Or were all those tests a false pass because that code was never ran? What I do now is open the log file of a test and manually check for prints from that TaskOrFunct_A() showing it executed. Risky, because I cannot guarantee that this happened in all of my 10,000 tests - in every regression kicked off.

I am used to define cover groups with cover points around some objects created by the TB (for example, I create a typedef and I check that all of its enumerated values are covered). But never thought whether something similar could be done on actual lines of codes inside the Testbench (not the DUT). Lines of code delimiting a task, a function, etc…. Essentially methods of classes representing TB agents. And then it all could be picked up and analyzed as part of the coverage collection flow.

Thank you so much for your kind help!

-Paolo

2

In reply to PaVi90:

Code coverage is manly a tool specific simulation analysis feature. Most simulation tools don’t distinguish between what code is for design and what code is for the testbench. However there might be some restrictions on certain language constructs for things like FSM analysis and toggle coverage.

Using code coverage to collect “functional” coverage in a TB has its challenges. For one thing, there is a lot of code in a TB that is never supposed to get executed unless there is an error or for aiding debug. There is also code enabling re-use that might check for conditions that might not be relevant in all situations

SystemVerilog does have covergroup syntax that triggers a sample when entering(begin) or exiting(end) a procedural block
module top;

class A;
 covergroup cg @@(begin testme);
    cp: coverpoint 1 {
    bins b = {1};
    }
  endgroup
  task testme;
    $display("%m");
  endtask 
  function new;
    cg = new;
  endfunction
endclass

A a =new;
initial begin
  $display($get_coverage);
  a.testme;
  $display($get_coverage);
  end
endmodule

But I think it is much simpler to use a immediate cover directive or sample a covergroup from inside the task.

3

In reply to dave_59:

Thank you Dave! I think I will go the route of sampling a covergroup from inside the task.

4

In reply to dave_59:

Hi! Regarding the usage of function in verilog code, can code coverage tool detect logic inside the function?

5

In reply to fatzcruz:

It can.