Verification Horizons

The Verification Horizons expands upon verification topics to provide concepts, values, methodologies and examples to assist with the understanding of what these advanced functional verification technologies can do and how to most effectively apply them.

In addition, the Verification Horizons Blog provides an online forum providing updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

March 2024

Enhancing PCIe Verification: How to Step Off the Map
Verification IP Mar 01, 2024 Irivinti Shiva Teja - Siemens Eda Article

This article intends to propose a range of strategies that an RC might use to ‘generate’ addresses that fall outside the standard scope, along with a detailed examination of the subtle complexities involved. Initially, we will explore two relatively simple methods to accomplish this. Following that, we will analyze the limitations inherent in these methods.
Tool Assisted Debug in Visualizer
Debug Mar 01, 2024 Richa Jha - Siemens Eda Article

Verification is one of the primary challenges in current times when designs are huge, and corresponding testbenches are equally large. Both the design and testbench work together to fulfill the desired expectations of the designer. Everything goes well until the simulation does not work as expected. This is where Visualizer, the debug platform, plays a crucial role in figuring out where the problem lies. Visualizer requires multiple databases to provide the debug features.
Maximize Returns on Your Hardware Emulation Investment with the Veloce Enterprise (ES) App
Acceleration Mar 01, 2024 Chuck Banken, Chenguang Li - Siemens Eda Article

Hardware-Assisted verification (HAV) with emulation is widely regarded as crucial for successfully designing, verifying, and deploying large ASICs and even FPGAs. An emulator is a major capital investment, and customers are highly motivated to get the maximum benefit from their expenditure.
Formal Verification: An Introduction and Exploration of Challenges
Formal Verification Mar 01, 2024 Yusuf Eren - Ankasys Article

Nowadays, the formal verification is getting more popular compared to the conventional simulation-based verification. The main idea behind the formal verification is to mathematically prove or disprove the correctness of a design with respect to the specification or requirement and ensure that the design behaves as intended under all possible scenarios. To achieve this, the formal verification tools are using Satisfiability Modulo Theories (SMT) solver engines.
A True Native 64-bit Vedic Multiplier Boosts Performance for Processors, Multi-Cores and DSP
Machine Learning Mar 01, 2024 Lakshya Miglani, Priyanka Gharat, Gopi Srinivas Deepala - Silicon Interfaces Article

This article introduces a revolutionary 64-bit native Vedic multiplier design, inspired by the Urdhva Tiryagbhyam sutra-based algorithm by Scientist Bharati Krishna Tirtha. The architecture offers superior power, timing, and area optimization, showcasing its potential for Processors, multi-cores, and DSPs computation needs. The differentiator between the current implementation and to past is the vastly enhanced native implementation of the algorithm.

July 2023

Whoops There Goes Another Config
Debug Jun 21, 2023 Rich Edelman Article

This is all made up. Except the true parts. It’s a murder mystery. Someone “murdered” my config setting – but I’m getting ahead of the story.We’re verification engineers, and our testbench is running just fine, doing the things it does, but the system is running a bit slower than our System Architects predicted.
Robustness Verification of ARINC708’s Manchester Codes in a DO-254 Project
Functional Safety Jun 21, 2023 Emin Akgün, Hilal Güneren - Ankasys Article

In this article, we will discuss the Display Data Bus of ARINC-708. The bus plays a critical role in terms of the pilot’s point of view. It requires a bi-phase Manchester encoding and decoding. For both Manchester coding and the bus protocol, some examples of possible error types are considered.
Mitigating System Failure Risks by verifying the Safeness of SafeSPI sub-module for the Automotive Industry
Functional Safety Jun 21, 2023 Gopi Srinivas Deepala, Himanshu Vishwakarma, Avnita Pal - Silicon Interfaces Article

This article outlines a systematic approach to attain safety objectives and create a conducive environment for achieving them. It includes a comprehensive inventory of alarms, faults, and their corresponding categories, all presented in a step-by-step format.

March 2023

Big Data Reimagines Verification Predictability and Efficiency
Planning & Analysis Feb 24, 2023 Darron May Article

Big data is a term that has been around for many years. The list of applications for big data is endless, but the process stays the same: capture, process, and analyze. With new, enabling verification solutions, big data technologies can improve your verification process efficiency and predict your next chip sign-off.
Democratizing Digital-Centric Mixed-Signal Verification Methodologies
Analog Mixed-Signal Feb 24, 2023 Sumit Vishwakarma Article

As the world of technology continues to evolve, the way we design and verify circuits is also evolving. The next-generation automotive, imaging, IoT, 5G, computing, and storage markets are driving the strong demand for increasing mixed-signal content in modern System-on-Chips (SoCs). Mixed-signal designs are a combination of tightly interwoven analog and digital circuitry. There are two main reasons for increased mixed-signal contents in today's SoC.
Lane Margining at Receiver and its Application Through Pipe Message Bus
Verification IP Feb 24, 2023 Sachin Mishra Article

PCI Express® (PCIe) announced its fourth generation (PCIe 4.0 standard) in year 2017.With PCIe Gen 3 the speed of operation was 8 GT/s (giga transfers per second) and error rate is manageable (10-12) but with doubling the frequency with each successive generations performance degradation become more pronounced due to variety of reasons like losses in the channels due to different components, reflections in the channel, jitter and cross talk between lanes in a multi-lane system.
The RISC-V Verification Interface (RVVI) – Test Infrastructure and Methodology Guidelines
Verification IP Feb 24, 2023 Aimee Sutton, Lee Moore, Kevin Mcdermott - Imperas Software Article

The open standard ISA of RISC-V is at the forefront of a new wave of design innovation. The flexibility to configure and optimize a processor for the unique target application requirements has a lot of appeal in emerging and established markets alike. RISC-V can address the full range of compute requirements such as an entry-level microcontroller, a support processor, right up to the state-of-the-art processor arrays with vector extensions for advanced AI applications and HPC.
A Formal-based Approach for Efficient RISC-V Processor Verification
Formal Verification Feb 24, 2023 Laurent Arditi, Paul Sargent, Thomas Aird, Lauranne Choquin - Codasip Article

The openness of RISC-V allows customizing and extending the architecture and microarchitecture of a RISC-V based core to meet specific requirements. This appetite for more design freedom is also shifting the verification responsibility to a growing community of developers. Processor verification, however, is never easy. The very novelty and flexibility of the new specification results in new functionality that inadvertently creates specification and design bugs.
Jumpstart your Formal Verification with a Little Help
Formal Verification Feb 24, 2023 Doug Smith Article

An advantage of using formal verification is how quickly a formal environment can be created with a few simple properties that immediately start finding design issues. However, not all design behaviors are easily modeled using SystemVerilog's property syntax, resulting in complex or numerous properties, or behaviors that require more than just SVA. Helper code can significantly reduce the complexity of properties as well as be used to constrain formal analysis.
Resolving Metastability Issues for Multi-clock SoC Environment for I2C
CDC Feb 24, 2023 Priyanka Changan, Darshan Sarode, Avnita Pal, Priyanka Gharat - Silicon Interfaces Article

This article aims to resolve metastability issues for multi-clock designs by noting the clock domains and the synchronization required for crossing the clock domains. The example SoC has an 8-bit simple Microcontroller and a Memory Module with a clock differently aligned (multi-clock) to the I2C Master and Slave. Leading to issues regarding metastability that needed to be resolved using synchronizers – currently two flip-flops using a closed-loop solution for sending and receiving clock domains.

December 2022

Out of the Verification Crisis - Improving RTL Quality
Planning & Analysis Dec 01, 2022 Harry Foster Article

A verification crisis is upon us that will not be solved solely through improvements in verification methodologies and techniques. The solution requires a holistic and philosophical change in the way we approach design with a foundation based on bug prevention. Our proposed first step in implementing this change tightly integrates static analysis into the design process, resulting in a decrease in bug density, which has a positive impact on downstream processes and consequently reduces cost.
Effective Resource Utilization in PCIe® Gen6: Shared Flow Control
Verification IP Dec 01, 2022 Vidushi Goel - Siemens Eda Article

In PCIe® 6.0, the data rate has doubled from 32 GT/s to 64 GT/s. This technology is a cost-effective and scalable interconnect solution that will continue to impact data-intensive markets like data centers, artificial intelligence/machine learning, HPC accelerators, and data center applications like high-end SSDs, automotive, IoT, and military/aerospace, while also maintaining backward compatibility with all previous generations of PCIe.
Data Integrity through TLP Encryption in PCI Express®
Verification IP Dec 01, 2022 Om Prakash - Siemens Eda Article

In today’s modern era, there has been an increase in the relentless push for higher-speed data transfers along with the security of the data to be transferred. The need for protecting the confidentiality of data is increasing day by day. The need to process higher data bandwidth is catered with the increased speed of PCIe®.
Missing Your Buttons and Menus? Create Your Own
Debug Dec 01, 2022 Vishal Baskar Article

Increasing efficiency while debugging involves having access to the right tools, permissions, and the ability to use the debug tool to its fullest. We know how engineers spend their time debugging rather than verifying. Provide them with all the features of a debugging tool, and they would not have exited the tool while enjoying debugging.
Application of AI/ML to Optimize Fault Simulation Coverage
Machine Learning Dec 01, 2022 Avnita Pal And Sastry Puranapanda - Silicon Interfaces® Article

Fault simulation replicates the typical sources of failures and analyzes them using the leading EDA tool. Testing is structured using fault simulator techniques to gain insight into fault effects and ensure defect coverage and quality testing are achieved. This article is based on standard fault Simulation and standard fault simulation techniques used in industry and applies intelligence and learning algorithms to reduce simulation cycles.
Understanding and Using Immediate Assertions
Assertions Dec 01, 2022 Ben Cohen Article

Immediate assertions are typically used to verify that expressions are within their required bounds, such as no overreach of the value of a counter or an illegal condition such a write without an enable. The action block is typically used for debug to display more information as to the cause of the error. However, immediate assertions can also be used to modify testbench variables for use in monitors or in other assertions, or to change the course of a testbench flow.

July 2022

Back to the Future with Formal Property Checking
Formal Verification Jul 05, 2022 Harry Foster Article

Back in 2010, I decided that instead of documenting a specific instance of applying formal property checking on a particular design, I would step back and look at the formal property checking process holistically. The goal was to define a set of repeatable steps that could be applied to any design. Fast forward to today, where I update the original by keeping the content that is still relevant and augmenting it with the new philosophies, methodologies, and technologies that have evolved since.
Getting to Know Visualizer - Part II
Debug Jul 05, 2022 Rich Edelman Article

Welcome to part 2 of our overview of the Visualizer Debug Environment, the user interface to debug, analyze and verify all our Siemens functional verification tools.As we saw in part 1, Visualizer is first and foremost a waveform debugger, with a host of other powerful debug capabilities also provided and supporting Verilog, SystemVerilog, VHDL, System C and C/C++. In this part of the article, we’ll look at driver tracing, X tracing, schematics, glitch debug, low power debug and more.
The Democratization of Digital Methodologies for AMS Verification
Analog Mixed-Signal Jul 05, 2022 Sumit Vishwakarma Article

A mixed-signal design is a combination of tightly interlaced analog and digital circuitry. Next-generation automotive, imaging, IoT, 5G, computing, and storage markets are driving the strong demand for increasing mixed-signal content in modern systems on chips (SoCs). There are two critical reasons for this trend.
Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces
Verification IP Jul 05, 2022 Himani Kaushik - Siemens Eda Article

Since the advent of digitalization, there has been an exponential growth in the volume of data. With this boost in the amount of data, hard disk drives (HDDs) could not sustain the data transfer rates, leading to bottlenecks in data access. Solid state drives (SSDs) have come to the forefront as a promising solution to our modern-day storage demands. SSDs are constantly evolving with upgrades of their critical components to provide high access speeds.
Bringing 5G NR Radio Frame Generation and Analysis to the Veloce® X-STEP™ Product Family
Acceleration Jul 05, 2022 Yrjö Keränen - Siemens Eda Article

Booming worldwide development activities for 5G NR create an increasing need for reference data and signal analysis. Recently launched Veloce X-STEP IQ Toolset (IQT) provides 3GPP compliant test data for radio unit (RU) testing needs. IQT workflow integrates with Siemens EDA tools such as Questa, Veloce and X-STEP. Being a standalone software solution, it is a cost-efficient solution to be installed in multiple workstations.
Speeding OTN Verification Using Emulation
Acceleration Jul 05, 2022 Pradeep Gupta, Saurabh Khaitan - Siemens Eda Article

In today's connected world, bandwidth requirements have shot up drastically due to the exponential growth in data communication. Optical Transfer Networks (OTN) today are the backbone of the tremendous amount of worldwide internet traffic. The ITU-T standards committee developed the OTN standard to address this data explosion with reliable infrastructure and low transmission costs in the optical world.
Reflections on Users’ Experiences with SVA - Part II
SystemVerilog Jul 05, 2022 Ben Cohen Article

During my years of contributions to the Verification Academy SystemVerilog Forum, I have seen many trends in real users’ difficulties in the application of assertions, and misunderstandings of how SVA works. In Part 1 of this article, I addressed the difficulties in expressing requirements for assertions, and clarified some critical SVA concepts concerning terminology, threads, and vacuity.
Easy Testbench Speedups
SystemVerilog Jul 05, 2022 Eileen Hickey - Doulos Inc. Article

As a Doulos ‘techie’, I train over 100 engineers in SystemVerilog and UVM each year. I do believe quite soundly, that the effort of simulation verification is an art, supported by the language. So, regardless of the language, I have a ready list of useful testbench coding strategies to achieve faster regression CPU cycle execution. This means more regression tests executed in the same amount of ‘wall-clock’ time!
Functional Safety Verification Challenges for Automotive ICs
Functional Safety Jul 05, 2022 Mihajlo Katona - Veriest Article

In a semiconductor world, functional safety is all about data storage and data movement through the system. Electrical or magnetic interference inside hardware systems can cause a single bit to flip to the opposite state spontaneously. And this is a typical case for random failure, which we desperately need to analyze and see its effects on the functional behavior of the system we are verifying.
The Path to a Safety Mechanism on an Unsafe PCIe® Sub-Module
Functional Safety Jul 05, 2022 Avnita Pal - Silicon Interfaces Article

This article illustrates the implementation of Safety Mechanisms on an unsafe PCIe® sub-module and demonstrates the use of Siemens EDA Austemper tools to generate Alarms for fault list detection and ensure Safety using a Duplication Mechanism.

March 2022

NVMe-oF – Simple, Invisible Fabric to Cloud Storage
Verification IP Mar 02, 2022 Dhruv Garg - Siemens Eda Article

In this era of digitalization, we can manage most of our personal stuff online, such as handling bank transactions, ordering clothes, and booking cab rides. The COVID-19 pandemic has pushed us even closer to digitalization. We are now ordering groceries online and entertaining ourselves through the plethora of content available on various streaming platforms. Inevitably, there has been significant growth in the amount of data available online and the number of users consuming it.
Getting to Know Visualizer - Part I
Debug Mar 02, 2022 Rich Edelman Article

The Visualizer Debug Environment is the user interface to debug, analyze and verify all our functional verification tools.Visualizer is first and foremost a waveform debugger. It also includes source code debug, transaction debug, C debug, driver tracing, X tracing, schematics, glitch debug, low power debug, and coverage analysis and coverage debug – all supporting Verilog, SystemVerilog, VHDL, System C, and C/C++.
Enabling Model-Based Design for DO-254 Certification Compliance
Functional Safety Mar 02, 2022 Jacob Wiltgen Article

Engineers can use Model-Based Design for requirements analysis, algorithm design, automatic HDL code generation, and verification to produce airborne electronic hardware that adheres to the DO-254 standard. The proposed Model-Based Design approach for DO-254 combines tools from MathWorks® and Siemens EDA for both design and verification. This workflow supports development phases from concept through implementation, streamlining development, and reducing costs.
How Do You “Qualify” Tools for DO-254 Programs?
Functional Safety Mar 02, 2022 Michelle Lange, Tammy Reeve - Patmos Engineering Services Article

Tools used in the design and verification of electronics have played a massive role in the dramatic evolution of these devices over the past few decades. After all, there is a limit to the amount of work and detail that even a good aerospace engineer can handle, but add the use of tools, and the sky (pun intended) is the limit.
Reflections on Users’ Experiences with SVA
SystemVerilog Mar 02, 2022 Ben Cohen Article

In my years of contributions to the Verification Academy SystemVerilog Forum, I have seen trends in real users’ difficulties in the application of assertions, the expression of the requirements, the angle of attacks for verification, the misunderstandings of how SVA works, and the confusion as to which SVA option to use.
A Faster Approach to Co-Simulation Using Questa and VPI
Simulation Mar 02, 2022 Vicente Bergas, Andrew Robertson, Marco Denicolai - Bitec Article

Co-simulating systems, including RTL and software, may often require excessive computational times if a cycle-accurate CPU model is used. However, many co-simulation exercises do not necessarily require precise CPU models and may benefit from the solution proposed here.This article presents a not-widely-used method of co-simulation that doesn’t need a cycle-accurate CPU simulation model and reduces simulation time while still allowing functional testing of software and RTL.
UVVM – VHDL Verification Methodology for Faster and Better FPGA and ASIC Verification
VHDL 2008 Mar 02, 2022 Espen Tallaksen - Emlogic Article

Verification takes half of a typical FPGA project’s development time. It is possible to significantly reduce this time with only minor adjustments and no extra cost while dramatically increasing the ability to reuse testbench components.An FPGA design’s architecture – from the top to the microarchitecture – is critical for both the FPGA quality and the development time. The same is true of the testbench.

September 2021

What Siemens’ Acquisition of OneSpin Means for Formal Verification – and You
Formal Verification Sep 01, 2021 Tom Fitzpatrick Article

Preface: in May 2021 Siemens EDA acquired OneSpin Solutions, combining Siemens' Questa Formal products and expertise (with roots and team members from 0-In) with OneSpin’s “apps first” approach to key growth markets including Trust&Security, Safety, RISC-V, and FPGAs. The combination adds to a cohesive Siemens EDA verification solution spanning simulation, formal, emulation, and prototyping.
Digital Thread, Digital Twin, and IC Development
Functional Safety Sep 01, 2021 Ray Salemi Article

In October of 2020, the Air Force challenged Aerospace and Defense industry to adopt the suggestions presented in the 2018 Digital Engineering Strategy. The document, named "There is No Spoon: The New Digital Acquisition Reality”, warns that aircraft design and deployment must embrace “the digital trinity” of Digital Engineering and Management, Agile Software Development, and Open Architecture.
Addressing the Trends and Challenges of Automotive IC Development
Functional Safety Sep 01, 2021 Ann Keffer Article

Developers of ICs, systems, and even vehicles are seeing some pretty significant shifts in the automotive industry. Recent estimates forecast that 50% of a vehicle’s Bill of Materials (BOM) will be electronics and electronic systems by the year 2030. Smart mobility is the root cause as the market demands features such as lane keep, adaptive cruise control, and emergency brake assist to name a few.
Deploying HLS in a DO-254/ED-80 Workflow
Functional Safety Sep 01, 2021 Tammy Reeve - Patmos Engineering Services Article

The adoption of tools into safety-critical workflows is often challenging as these new technologies must demonstrate sufficient safeness to use before being deployed in production environments. The demand for High-Level Synthesis capabilities within DO-254 projects is growing and this paper describes the requirements and considerations to successfully use High-Level Synthesis within a DO-254 workflow.
Hardware-Assisted Verification Through the Years
Acceleration Sep 01, 2021 Jean-Marie Brunet Article

A quick glance in today’s design verification toolbox reveals a variety of point tools supporting the latest system-on-chip (SoC) design development. When combined and reinforced by effective verification methodologies, these tools trace even the most hard-to-find bug, whether in software or in hardware. The focus on tools and delivering a tightly woven integration between complementary tools is a strategic focus at Siemens EDA.
Veloce Hardware-Assisted Verification – Complete, Unified, and Progressive
Acceleration Sep 01, 2021 Jean-Marie Brunet Article

Despite abundant rumors predicting the end of life for Moore’s Law (the axiom stating transistor density doubles every 24 months), semiconductor design sizes continue to grow exponentially with no end in sight. In the process, design sizes push costs off the roof.According to market research International Business Strategies (IBS), the total cost of designing a state-of-the-art system on chip (SoC) at the 5nm process technology node exceeds half a billion dollars.
Veloce Prototyping Solutions Accelerate Verification of HPC AI-Enabled SoCs
Acceleration Sep 01, 2021 Stephen Bailey Article

In a 2010 inaugural issue of the report from the UK High Performance Computing Special Interest Group (HPC-SIG), the following statement resonated with a large number of companies and research institutions that were using HPC technology."Over the past decade there has been a revolution in High Performance Computing spearheaded by a movement away from using expensive traditional proprietary supercomputers to systems based on relatively inexpensive commodity off-the-shelf systems." [1]
"Hug the Debug" – Before It’s Too Late
Debug Sep 01, 2021 Sumit Vishwakarma Article

Though the term “shift-left” originated in the software industry, its importance is often cited in the hardware (semiconductor) industry where the end-product (chip) costs are skyrocketing. The increase in cost is driven by the global chip shortage, especially in the automotive industry.
Questa Visualizer Adds Coverage Analysis to the Platform
Debug Sep 01, 2021 Yara Esam - Siemens Eda Article

Questa Visualizer Debug is our high performance, scalable, context-aware debugger supporting the complete logic verification flow including simulation, emulation, prototyping, testbench, low-power, and assertion analysis. Intuitive and easy to use, Visualizer improves debug productivity of today's complex SoCs and FPGAs.
Verifying a DDR5 Memory Subsystem
Verification IP Sep 01, 2021 Kamlesh Mulchandani Article

The latest technologies and applications often demand more speed and performance. With the advancement in technologies such as multi-core CPUs and GPUs, the need for faster data processing is becoming a bottleneck for system performance. Applications such as Machine Learning and Data Centers rely upon high performance and lower latency. These applications need a memory that can offer high speed, better performance, high density, lower latency, and data integrity.
Expediting Simulation Turn-around Time with Incremental Build Flow
Simulation Sep 01, 2021 Neil Johnson Article

Rapid simulation turn-around time is critical for high-functioning SoC teams because it enables a tight feedback cycle that teams use to constantly validate progress. Whether the result is a failed compile, passing simulation or anything in between, the sooner you get that result, the sooner you get to the next step and closer you get to your ultimate objective: passing silicon.
Standards Participation at Siemens EDA
Standards Sep 01, 2021 Dave Rich Article

All of us are involved with standards every day whether we realize it or not. From the day we are born, we interact with standards. In the US, a baby receives a standardized health assessment score called Apgar after 1 minute. You are weighed and measured to standards. You wear clothes sized to standards. Eventually, you learn to read and write according to some culturally accepted standards.

March 2021

Celebrating 10 Years of the UVM
UVM Mar 03, 2021 Mark Peryer Article

Version 1.0 of the UVM class library was released by Accellera at the end of February 2011, the result of a unique collaborative effort between fierce competitors (Siemens EDA, formerly Mentor Graphics, Cadence, and Synopsys) and a small number of activist user companies. The objective was to provide an industry standard SystemVerilog based verification methodology.
Purging CXL Cache Coherency Dilemmas
Verification IP Mar 03, 2021 Nikhil Jain, Gaurav Manocha - Siemens Eda Article

The massive growth in the production and consumption of data, particularly unstructured data, like images, digitized speech, and video, results in an enormous increase in accelerators' usage. The growing trend towards heterogeneous computing in the data center means that, increasingly, different processors and co-processors must work together efficiently, while sharing memory and utilizing caches for data sharing.
What is “Verification” in the Context of DO-254 (Avionics) Programs?
Functional Safety Mar 03, 2021 Michelle Lange, Jeff Reeve And Tammy Reeve - Patmos Engineering Services Article

If you are a hardware design or verification engineer, you probably have a good idea of what verification entails. However, add compliance to RTCA/DO-254 as a requirement, and suddenly the definition of “verification” may not be so clear. First, the term “verification” must be understood alongside the synergistic term “validation.” Next, in a DO-254 context, verification spans a wider scope than it does traditionally, so understanding this is crucial.
Formal Etiquette for Code Coverage Closure
Formal Verification Mar 03, 2021 Ajeetha Kumari, Arunachalam R And Satheesh Ethiraj - Verifworks Article

Coverage closure is a key step in any IP design verification project. Code coverage is a much-needed metric in most modern-day IP designs. It helps teams to ensure that all RTL code written is indeed exercised and verified prior to tape-out. Without such a guarantee, a semiconductor design house may well be risking millions of dollars in a potential bug-escape to silicon. As the process of code coverage is well automated, it is widely used in the industry.
A Formal Verification Technique for Complex Arithmetic Hardware
Formal Verification Mar 03, 2021 Dr. Sam Elliott - Imagination Technologies Article

With more emphasis within the electronics industry on high-performance and shorter time to market, the need for high-confidence and high-quality end-to-end verification is becoming more and more important. This is especially true on the heavily optimized arithmetic datapath blocks most used in modern compute and neural network applications. Missed bugs can delay projects and be costly to reputations, and, at the very least, be likely to sap performance.
Predictable and Scalable End-to-End Formal Verification
Formal Verification Mar 03, 2021 Dr. Ashish Darbari Article

In this article, we discuss why formal verification adoption has been limited in industry, and how abstraction-based methodology in formal verification can help DV engineers become successful in adopting formal property checking more widely. Abstraction is the key to obtaining scalability and predictability. It provides an efficient bug-hunting technique and helps in establishing exhaustive proof convergence.
Enabling RISC-V Based System Development
Verification IP Mar 03, 2021 Sandeep Nasam, Sagar Thakran - Logic Fruit Technologies Article

This article focuses on providing a jump start on RISC-V development. It shows how to build a verification environment quickly involving a RISC-V core and required peripherals based on selected applications.
The Six Steps Of RISC-V Processor Verification Including Vector Extensions
Verification IP Mar 03, 2021 Larry Lapides Article

The open standard ISA of RISC-V allows SoC developers to also build or modify a processor core optimized to the application requirements. The SoC verification tasks are adapting to address the significant increases in complexity. This article covers the 6 key components of RISC-V processor verification: The DV Plan, RTL DUT, Testbench, Tests, Reference model, and Siemens EDA Questa SystemVerilog simulation environment.

November 2020

Quantifying FPGA Verification Effectiveness
FPGA Verification Oct 26, 2020 Harry Foster Article

The 2019 global semiconductor market was valued at $385.4 billion after experiencing a 15% decline due to a 32% drop in the memory IC market, which is expected to recover in 2021[1]. The FPGA portion of the semiconductor market is valued at about $5 billion[2]. The FPGA semiconductor market is expected to reach a value of $7.5 billion by 2030, growing at a compounded annual growth rate (CAGR) of 4.4% during this forecast period.
Arasan MIPI® CSI-2-RX IP Verification Using Questa Verification IPs
Verification IP Oct 26, 2020 Vikas Sharma - Siemens Eda Article

This article describes the verification process of the ARASAN MIPI® CSI-2-RX IP core using Questa Verification IPs.
Memory Softmodels - The Foundation of Validation Accuracy
Verification IP Oct 26, 2020 Ridham Kothari - Siemens Eda Article

As always, we must continue to reduce the time-to-market of SoCs and complex systems. An FPGA prototype implementation of these systems can be used as a basis for early software or firmware development, hardware-software co-verification and system validation, and all this can be achieved before actual silicon is available.
Increasing Functional Coverage by Automation for Zetta-Hz High Speed CDMA Transceiver
Coverage Oct 26, 2020 Karthik Bandaru, Priyanka Gharat, And Sastry Puranapanda - Silicon Interfaces® Article

The efforts to apply constrained randomization to create test cases is based on the developer or verification engineer’s perception of what test vectors are required and can easily lead to hidden bugs being overlooked. Traditionally, the coverage goals would have been reached by writing more test cases with unpredictable schedules, often impacting time-to-market goals. Functional coverage defines critical states and constrained randomization tests those states in unpredictable ways.
Unified Approach to Verify Complex FSM
Verification IP Oct 26, 2020 Milan Patel - Einfochips, Ltd (An Arrow Company) Article

The purpose of this article is to share a strategy on how to verify any simple or complex FSM in an organized, robust, manageable, and efficient way. To verify such FSMs thoroughly we need random scenarios that cover all the possible state transition conditions, corner and boundary conditions, and relevant functional behavior. For that, we require a strong base entity that helps to generate random scenarios to cover all FSM entry-exit conditions and erroneous scenarios easily.
RISC-V Design Verification Strategy
Verification IP Oct 26, 2020 Dr. Mike Bartley Article

As the RISC-V architecture becomes increasingly popular, it is being adopted across a diverse range of products. From the development of in-house cores with specialized instructions, to functionally safe SoCs and security processors for a variety of verticals – RISC-V adoption brings several verification challenges that are discussed in this article, along with potential approaches and solutions.

July 2020

Formal Is The “New Normal” - Deploy These FV Apps In Your Next Project
Formal Verification Jul 19, 2020 Ajeetha Kumari, Hemamalini Sundaram, And Darshan Ballari, Verifworks, Llc And Cvc Pvt., Ltd. Article

Formal verification is now pervasive in many chip design verification projects. Key to this widespread adoption is the availability of automated “apps” that makes it easy to deploy Formal in hitherto simulation-only projects. We at VerifWorks have a long history of formal deployment at many design houses and have seen the challenges engineers face while adopting the same. We have also trained hundreds of engineers to use Formal with ABV (Assertion-Based Verification) through CVC.
Understanding the SVA Engine Using the Fork-Join Model
SystemVerilog Jul 19, 2020 Ben Cohen Article

SVA (SystemVerilog Assertions) is a powerful short-handed assertion language with many constructs; it is built as an integral part of SystemVerilog but with a specific syntax and sets of rules. Unlike a scoreboard that tends to focus on a model implementation that mimics the DUT, SVA addresses the requirements; that brings out a better understanding of the requirements, along with its weaknesses for lack of definitions.
Bridging the Portability Gap for UVM SPI VIP Core Reuse From IP to Sub-System and SoC
UVM Jul 19, 2020 Kiran Malvi, Priyanka Gharat, Past Dean Prof Sastry Puranapanda - Silicon Interfaces® Article

This article focuses mostly on the vertical reuse of the test intent from IP-block to Sub-System and study of reusability from Sub-system to SoC level. The example taken to demonstrate vertical reusability is a single master and slave SPI Core IP configuration. A UVM layered testbench is wrapped around the design to verify and validate proper functioning of SPI Core IP.
PCIe® Simulation Speed-Up with PLDA PCIe® Controller for DMA Application
Verification IP Jul 19, 2020 Akshay Sarup Article

PCI Express® (PCIe®) is a dominant technology for hardware applications requiring high-speed connectivity between networking, storage, FPGA, and GPGPU boards to servers and desktop systems. It is a robust technology that has evolved over decades to keep up with advancements in throughput and speed for I/O connectivity for computing requirements.
Addressing VHDL Verification Challenges with OSVVM
VHDL 2008 Jul 19, 2020 Jim Lewis Article

Most people don't think of VHDL as a verification language. However, with the Open Source VHDL Verification Methodology (OSVVM) utility and verification component libraries it is. Using OSVVM we can create readable, powerful, and concise VHDL verification environments (testbenches) whose capabilities are similar to other verification languages, such as SystemVerilog and UVM.
Extending SoC Design Verification Methods for RISC-V Processor DV
Verification IP Jul 19, 2020 Larry Lapides Article

As SoC developers adopt RISC-V and the design freedoms that an Open ISA (Instruction Set Architecture) offers, DV teams will need to address the new verification challenges of RISC-V based SoCs. The established SoC verifications tasks and methods are well proven, yet depend on the industry wide assumption of ‘known good processor IP’ based on the quality expectations associated with IP providers such as Arm or MIPS Technologies.
Effective Validation Method of Safety Mechanism Compliant with ISO 26262
Functional Safety Jul 19, 2020 Toshiyuki Hamatani - Verification Technology, Inc. Article

The metrics to measure the effectiveness of Safety Mechanisms include code coverage rate, SPFM (Single- point failure metric) and LFM (Latent failure metric). Especially in SPFM and LFM, if the specified value is not reached on the Fault Injection Simulation (using Gate Level) at the end of verification, it will cause iterations, which will cause a significant increase in time and cost compared to consumer LSIs.

December 2019

Why Hardware Emulation Is Necessary to Verify Deep Learning Designs
Acceleration Dec 03, 2019 Jean-Marie Brunet Article

There is no doubt that computers have changed our lives forever. Still, as much as computers outperform humans at complex tasks such as solving complex mathematical equations in almost zero time, they may underperform when solving what humans can do easily — image identification, for instance. Anyone in the world can identify a picture of a cat in no time at all. The most powerful PC in the world may take hours to get the same answer.
Deadlock Prevention Made Easy with Formal Verification
Formal Verification Dec 03, 2019 Dr. Jeremy Levitt Article

You are about to go into a planning meeting for a new project when you get a call from one of your company’s Customer Advocate Managers: a product that you worked on just started shipping in volume, and there are a growing number of field reports that the system randomly freezes-up after a few weeks in operation. While a soft reset “works,” it will run anywhere from 5 to 10 days before it has to be rebooted again.
Exercising State Machines with Command Sequences
Standards Dec 03, 2019 Matthew Ballance Article

Almost every non-trivial design contains at least one state machine, and exercising that state machine through its legal states, state transitions, and the different reasons for state transitions is key to verifying the design’s functionality. In some cases, we can exercise a state machine simply as a side-effect of performing normal operations on the design.
Designing A Portable Stimulus Reuse Strategy
Standards Dec 03, 2019 Matthew Ballance Article

The PSS language was designed with the requirements of test intent reuse, and automated test creation in mind. The requirement to allow test intent to be reused across a variety of very different platforms drove the PSS language to enable a clean and clear distinction between test intent and test realization, as shown in Figure 1. In a PSS description, test intent specifies the high-level view of what behavior is to be exercised.
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon
CDC Dec 03, 2019 Kurt Takara Article

In this article, we will discuss the difficulties encountered with traditional CDC protocol verification methodologies and present a complete methodology to overcome the current challenges.

March 2020

Verify Thy Verifyer
UVM Mar 01, 2020 Srinivasan Venkataramanan, Ajeetha Kumari - Verifworks Article

Design Verification is a field that requires a lot of thinking and equally a lot of coding. Tighter time-to-market adds a lot of schedule pressure to the teams coding those testbenches and test cases.The advent of UVM (Universal Verification Methodology) as the standard framework, has helped the industry make good progress in terms of structured testbenches. One of the primary objectives of UVM is to build robust, reusable testbenches.
Using Questa SLEC to Speed Up Verification of Multiple HDL Outputs
Formal Verification Mar 01, 2020 Tomáš Vaňák - Codasip Article

Questa SLEC, the formal analysis app from Siemens EDA, was designed to automatically compare a block of code ("specification" RTL) with its functional equivalent that has been slightly modified ("implementation" RTL), helping design teams save considerable amounts of time and resources. Codasip, the leading provider of configurable RISC-V® IP, has come up with a new use of this tool: the verification team uses it to compare a fully UVM-verified HDL code.
AI-Based Sequence Detection
Machine Learning Mar 01, 2020 Asif Ahmad And Abhishek Chauhan, Agnisys Article

In this era of automation, significant advantages can be gained by automatically generating verification and validation sequences from natural language text using artificial intelligence (AI) based sequence detection techniques, and then using those sequences in C/UVM code. This article talks about the current state of development in this area and gives ideas about how you can implement your own solution to achieve true specification-driven software development.
An Open Data Management Tool for Design and Verification
Verification Management Mar 01, 2020 Vishal Patel, Manoj Pandey - Arastu Systems Article

The Big Data technology has evolved to handle both volume and velocity of data, currently being generated by the chip design and verification activities. The core challenge of effective data management and hence actionable insight generation is still not available to the industry in the true sense. Connecting data islands as created by various tools in various formats across digital design and verification workflows and creating a Unified Data Lake is an important missing piece.
Detecting Security Vulnerabilities in a RISC-V® Based System-on-Chip
Verification IP Mar 01, 2020 Dr. Nicole Fern - Tortuga Logic Article

Modern electronic systems are complex, and economics dictate that the design, manufacturing, testing, integration and deployment of Application Specific Integrated Circuits (ASICs), System on Chips (SoCs) and Field Programmable Gate Arrays (FPGAs) span companies and countries. Security and trust in this diverse landscape of 3rd party IP providers, processor vendors, SoC integrators and fabrication facilities, is both challenging and introduces security risks.
Formal Verification of RISC-V® Processors
Formal Verification Mar 01, 2020 Dr. Ashish Darbari Article

The verification of modern-day processors is a non-trivial exercise, and RISC-V® is no exception. In this article, we present a formal verification methodology for verifying a family of RISC-V® “low-power” processors. Our methodology is both new and unique in the way we address the challenges of verification going beyond just functional verification.

March 2018

Configuring Memory Read Completions Sent by PCIe® QVIP
Verification IP Mar 01, 2018 Arushi Jain, Rajat Rastogi - Siemens Eda Article

In real hardware systems, the read completion sizes for upstream read requests (initiated towards the root complex) are characteristics of the processor in use and the maximum payload size (request payload size) limitations of endpoint as a receiver. Out of various aspects to be considered while creating a read completion, important aspects of data associated with it are byte enables (valid data to be read), value of the read request, and address at which the request is initiated.
SATA Specification 3.3 Gaps Filled by SATA QVIP
Verification IP Mar 01, 2018 Naman Saxena, Nitish Goel, Rajat Rastogi - Siemens Eda Article

Developed to supersede Parallel ATA (PATA), the Serial ATA (SATA) protocol provides higher signaling rates, reduced cable sizes, and optimized data transfers for the connections between host bus adaptors and mass storage devices. SATA is a high-speed serial protocol with a point-to-point connection between the host and each of its connected devices. It is a layered protocol comprising of a command and application layer, transport layer, link layer, and physical layer.
From Power Intent to Microarchitectural Checks of Low-Power Designs - Part 1
Low Power Mar 01, 2018 Progyna Khondkar Article

PA-Static verification is primarily targeted to uncover the power aware structural issues that affects designs physically in architectural and microarchitectural aspects. The structural changes that occur in a PA design are mostly due to physical insertions of special power management and MV cells; such as power switches (PSW), isolation (ISO), level shifter (LS), enable level shifter (ELS), repeaters (RPT), and retentions flops (RFF).
SVA Alternative for Complex Assertions
SystemVerilog Mar 01, 2018 Ben Cohen Article

This article first explains the concepts, and then by example, how a relatively simple assertion can be written without SVA with the use of SystemVerilog tasks; this provides the basis for understanding the concepts of multithreading and exit of threads upon a condition, such as vacuity or an error in the assertion, providing examples that demonstrate how some of the SVA limitations can be overcome with the use of tasks, but yet maintain the spirit (but not vendor’s implementations) of SVA.
A Hierarchical and Configurable Strategy to Verify RISC-V based SoCs
Verification IP Mar 01, 2018 Dr. Mike Bartley Article

This article outlines a hierarchical and configurable verification strategy for RISC-V based IP and SoCs. A three-level (unit, core and SoC) hierarchy is proposed for testbenches. Each level of the hierarchical testbench is configurable for both architectural and micro-architectural parameters. At the heart of the verification strategy is an ISG (Instruction Stream Generator) and a UVM testbench.

November 2015

Memories Are Made Like This
Verification IP Nov 01, 2015 Mark Peryer Article

One of the most common requirements for the verification of a chip, board or system is to be able to model the behavior of memory components, and this is why memory models are one of the most prevalent types of Verification IP (VIP).
A New Stimulus Model for CPU Instruction Sets
Coverage Nov 01, 2015 Staffan Berg, Mike Andrews - Siemens Eda Article

Verifying that a specific implementation of a processor is fully compliant with the specification is a difficult task. Due to the very large total stimuli space it is difficult, if not impossible, to ensure that every architectural and micro-architectural feature has been exercised. Typical approaches involve collecting large test-suites of real SW, as well as using program generators based on constrained- random generation of instruction streams, but there are drawbacks to each.
On-Chip Debug – Reducing Overall ASIC Development Schedule Risk
Debug Nov 01, 2015 Eric Rentschler - Siemens Eda Article

With ASIC complexity on the increase and unrelenting time-to-market pressure, many silicon design teams still face serious schedule risk from unplanned spins and long post-silicon debug cycles. However, there are opportunities on both the pre-silicon and post-silicon sides that can be systematically improved using on-chip debug solutions.
Hardware Emulation: Three Decades of Evolution—Part III
Acceleration Nov 01, 2015 Dr. Lauro Rizzatti - Rizzatti Llc Article

At the beginning of the third decade, circa 2005, system and chip engineers were developing evermore complex designs that mixed many interconnected blocks, embedded multicore processors, digital signal processors (DSPs) and a plethora of peripherals, supported by large memories. The combination of all of these components gave real meaning to the designation system on chip (SoC).
QVIP Provides Thoroughness in Verification
Verification IP Nov 01, 2015 Kiran Sharma, Vipin Kumar - Agnisys Technology Pvt. Ltd. Article

The present day designs use standard interfaces for the connection and management of functional blocks in System on Chips (SoCs). These interface protocols are so complex that, creating in-house VIPs could take a lot of engineer’s development time. A fully verified interface should include all the complex protocol compliance checking, generation and application of different test case scenarios, etc.
A Generic UVM Scoreboard
UVM Nov 01, 2015 Jacob Andersen, Kevin Seffensen, Peter Jensen - Syosil Aps Article

All UVM engineers employ scoreboarding for checking DUT/reference model behavior, but only few spend their time wisely by employing an existing scoreboard architecture. The main reason is that existing frameworks have inadequately served user needs and have failed to improve user effectiveness in the debug situation. This article presents a better UVM scoreboard framework, focusing on scalability, architectural separation and connectivity to foreign environments.

February 2013

Bringing Verification and Validation under One Umbrella
Acceleration Feb 22, 2013 Hans Van Der Schoot Article

The standard practice of developing RTL verification and validation platforms as separate flows, forgoes large opportunities to improve productivity and quality that could be gained through the sharing of modules and methods between the two. Bringing these two flows together would save an immense amount of duplicate effort and time while reducing the introduction of errors, because less code needs to be developed and maintained.
System Level Code Coverage using Vista Architect and SystemC
Coverage Feb 22, 2013 Ken P. Mccarty - Siemens Eda Article

SoC are constantly becoming more and more complex forcing design teams to eke out as much performance as possible just to stay competitive. Design teams need to get it right from the start and can't wait until it's built to find out how it truly performs. This is where System Level Modeling and SystemC/TLM shine.
The Evolution of UPF: What’s Next?
Low Power Feb 22, 2013 Erich Marschner Article

Usage of the Unified Power Format (UPF) is growing rapidly as low power design and verification becomes increasingly necessary. In parallel, the UPF standard has continued to evolve. A previous article1 described and compared the initial UPF standard, defined by Accellera, and the more recent IEEE 1801-2009 UPF standard, also known as UPF 2.0. The IEEE definition of UPF is the current version of the standard, at least for now, but that is about to change.
Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features
SystemVerilog Jun 12, 2014 Ajeetha Kumari, Srinivasan Venkataramanan - Cvc Pvt. Ltd. Article

SystemVerilog has become the most widely deployed Verification language over the last several years. Starting with the early Accellera release of 3.1a standard, the first IEEE 1800-2005 standard fueled the widespread adoption in tools and user base. Since 2005 there is no look-back to this "all encompassing" standard that tries to satisfy and do more for RTL Designers and Verification engineers alike.
SVA in a UVM Class-based Environment
SystemVerilog Feb 22, 2013 Ben Cohen Article

This article demonstrates how SVA complements a UVM class-based environment. It also demonstrates how the UVM severity levels can be used in all SVA action blocks instead of the SystemVerilog native severity levels.
The Formal Verification of Design Constraints
Formal Verification Feb 02, 2013 Ajay Daga - Fishtail Design Automation Article

There are two approaches to the verification of design constraints: formal verification and structural analysis. Structural analysis refers to the type of analysis performed by a static timing tool where timing paths either exist or not based on constant settings and constant propagation.