Writing sequences in UVM

UVM
,
1

Dear Members,

Please suggest me in writing the sequences for the following scenario.
one mode bit we need to set as rand and if that bit is one we need to send 3 sequences i.e write followed by read and followed by write (WRW), if that bit is zero we need to send all 3 write sequences(WWW). how can we implement this ?

Thanks in advance
Naveen

2

To write sequences you can look at the following link.
UVM Sequences Session

3

In reply to Ashith:

Thanks Ashith
If possible can you please provide the suggestion for the above mentioned scenario

Regards
Naveen

4

Crearte seperate WRITE and READ sequence.
Create a top level sequence that will call WRW or WWW base on a rand mode bit.
In the testcase create-randomize-start the top level seq.Based on the mode bit generated WRW or WWW will be executed.

class top_level_seq extends uvm_sequence #(my_trasn);
  rand bit mode;
  wr_seq wr_seq_h;
  read_seq read_seq_h;
  
  task body();
  //WRW
  if(mode==1) begin : WRW
    wr_seq_h = wr_seq::type_id::create("wr_seq_h"); 
    wr_seq_h.start(SQR);
    read_seq_h = read_seq::type_id::create("read_seq_h"); 
    read_seq_h.start(SQR);
    wr_seq_h = wr_seq::type_id::create("wr_seq_h"); 
    wr_seq_h.start(SQR);
  end : WRW
  
  //WWW
  else begin : WWW
     repeat(3) begin
       wr_seq_h = wr_seq::type_id::create("wr_seq_h"); 
       wr_seq_h.start(SQR);
     end
  end : WWW
  endtask

endsequence : top_level_seq

Hope you got an idea

5

In reply to georgean:

Just different try , please take care of syntactic errors.



class top_level_seq extends uvm_sequence #(my_trasn);
  rand bit mode;
  rand bit[2:0] seq_order;
  
   constraint con_seq_oder
  {
    solve mode before seq_order;
    if(mode==1)
    seq_order=3'b101;
   else
    seq_order=3'b111;
  } 
 
  wr_seq wr_seq_h;
  read_seq read_seq_h;
 
  task body();
  //WRW
   foreach(seq_order[i])
begin
  if(seq_order[i]==1) begin : WRW
    wr_seq_h = wr_seq::type_id::create("wr_seq_h");
   wr_seq_h.start(SQR);
    end
 else
    begin
    read_seq_h = read_seq::type_id::create("read_seq_h"); 
    read_seq_h.start(SQR);
  end 
end
endsequence : top_level_seq
6

In reply to cool_cake20:

Hi cool_cake20,

Thanks for the solution.
If we need to create a top_level_seq that creates any random pattern of write and read how will we do it?
For eg: if the top_level_seq has to create WWR patten can we pass 110 to seq_order[2:0] as shown below?

In testcase run_phase -

task run_phase();
  //raise obj
  top_level_seq_h = top_level_seq::type_id::create("top_level_seq_h");
  top_level_seq_h.con_seq_oder.constraint_mode_off(0);
  top_level_seq_h.randomize() with { top_level_seq_h.seq_order=3'b110; }
  top_level_seq_h.start(SQR);
  //drop obj
endtask : run_phase

Thanks.

7

In reply to georgean:

Small correction(if the above one works it’s fine).
You are trying to do inline constraint on random variable which you have disabled.
Just assign seq_order after object creation.



task run_phase();
  //raise obj
  top_level_seq_h = top_level_seq::type_id::create("top_level_seq_h");
  top_level_seq_h.con_seq_oder.constraint_mode_off(0);
   top_level_seq_h.con_seq_oder=3'b110
  top_level_seq_h.randomize(); 
  top_level_seq_h.start(SQR);
  //drop obj
endtask : run_phase

one more way


task run_phase();
  //raise obj
  top_level_seq_h = top_level_seq::type_id::create("top_level_seq_h");
  top_level_seq_h.randomize(); 
  top_level_seq_h.con_seq_oder=3'b110;// i don't care what resulted in randomization , i am going to override it.
  top_level_seq_h.start(SQR);
  //drop obj
endtask : run_phase
8

In reply to cool_cake20:

Thank you.