Writing to a register using UVMREG model with reg name passed by user

UVM
1

Hi,

I have a UVM_REG model called my_reg_model. To do normal reads or writes, I would use my_reg_model.REG_NAME_REG0.write(uvm_reg_status,write_data);.
I want to add a task where the user can pass the name of the register (REG_NAME_REG0 in above example) and value to be written as input arguments, something like the below.

task base_seq::reg_write_task(string reg_name, bit [31:0] write_data);
`WRITE_REG(reg_name, write_data)
endtask

I tried using a macro, like below, but this results in error during elaboration as this evaluates to my_reg_model.reg_name.write( …) and “reg_name” is not a real register in the reg model.
`define WRITE_REG(reg_name,write_data) my_reg_model.reg_name.write(uvm_reg_status, write_data);

What would be the correct way to do this? Any suggestions appreciated. Thank you!

2

In reply to SPinDV:

You cannot use strings to form variable names. But the UVM REG model is set up with strings in its database that you can look up a handle to the register.

task base_seq::reg_write_task(string reg_name, bit [31:0] write_data); 
  uvm_reg reg_h = my_reg_model.get_reg_by_name(reg_name);
  if (reg_h == null) 
      `uvm_fatal("reg_write_task", $sformatf("Could not find %s",reg_name))
  reg_h.write(uvm_reg_status, write_data);
  
endtask
3

Thank you! That worked for me.