Why non blocking while driving signals on interface

UVM
1

Hi,

1)when we driving on interface through clocking block and assignment is blocking,it is giving error. Can you pls tell me why
2) not using clocking block and assignment is non blocking.
3) using clocking block and assignment is non blocking.

when we will use 2) when we will use 3)

2

Please read section 14.16.1 Drives and nonblocking assignments in the 1800-2012 LRM for the answer to 1).

If you have used Verilog for designs and testbenches, you should already understand the difference between blocking and non-blocking assignments, how to drive bidirectional wires, and how to deal with signal skews. This is typical Verilog module-to-module communication. You can do Verilog module-to-testbench communication the same way.

In a class-based SystemVerilog testbench, many verification engineers are not experienced with the module communication issues that designer is faced with. Also, it is not possible to assign to wires directly from a class, making bidirectional communication difficult.

The clocking block has its origin in Vera, where the testbench and design are written in separate languages. The Vera clocking block was the glue between the testbench and the DUT, and hid all the physical timing details from the testbench writer. (it was actually called an interface in Vera, but that keyword already used for a related construct in SystemVerilog)

If you already understand Verilog module-to-module communication, then a clocking block may seem like an extra layer, but it does provide some safety in accessing the DUT (can only read signals declared as inputs, and only drive signals declared as output. So the recommendation on when to use 2) or 3) is really based on your comfort level around the use of either, and is up to you. My only strong recommendation is to stay with one choice and not mix the two styles.

3

In reply to dave_59:

See the posts about interfaces in
https://forum.verificationacademy.com/forum/verification-methodology-discussion-forum/systemverilog-and-other-languages-forum/31265-assigning-interface-net-type-signa
Ben Cohen SystemVerilog.us