What will be the verification scenarios for testing a memory model?

UVM
1

Suppose we have a memory model, i am looking at various checks that can be performed to verify the memory model.

  1. single read and write
  2. back to back reads and writes to same address/different addresses.
  3. read followed by write to same address/different address.
  4. verify boundary locations of memory using reads /writes
  5. verify different data patterns, walking 1’s, all 0’s, random data

What else can be done?

What will the methods/functions that can be present in a system verilog memory model BFM class? and how to implement them…

Please provide your inputs?

1 Like
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In reply to n347:
Probably ideas can be discussed here but the implementation would be very much design specific

  • Apart from the ones you mentioned above you could also check frontdoor write and backdoor read. This would catch issues in address translation. Say if there is same bug in address translation in write path and read path if you do frontdoor write and frontdoor read, you can’t be sure if it landed in the right place of the memory
  • If the memory has shutdown, sleep modes you may have to verify them as well especially in gate-level simulations
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In reply to Subrahmanyam:

I’d say there is no common approach. Scenarios are depending on the memory types. If you have a DDR4 there will be different scenarios than for a simple SRAM.
You might know DDR have a lot of functionaöities.