What does it mean to pass uvm_object_wrapper in uvm_config_db?

UVM
1

Hello,

What do we mean when we pass uvm_object_wrapper in the UVM environment for setting a default sequence to be executed in a specific phase? Usually we pass the “type” in the #(),
does it mean uvm_object_wrapper is the “type” of the sequence?

Example :
uvm_config_db #(uvm_object_wrapper)::set(this, “i_agt.sqr.reset_phase”, “default_sequence”, router_input_port_reset_sequence::get_type());

I see this usage so far only in env files, is there any other place where we could pass uvm_object_wrapper in #()?

Thanks.

2

In reply to UVM_beginner:

According to the UVM Coding Guidelines, do not use reset_phase.
Second, you should not use the uvm_config_db to set the default_sequence for any phase. Instead, you should specify the default sequence to be executed during the run_phase of your base test. Then you can use a derived test to execute any other sequences you want to execute during run_phase. You can also use the factory to change the default sequence either via an override in the derived test of via the command line.

3

In reply to tfitz:

In reply to UVM_beginner:
According to the UVM Coding Guidelines, do not use reset_phase.
Second, you should not use the uvm_config_db to set the default_sequence for any phase. Instead, you should specify the default sequence to be executed during the run_phase of your base test. Then you can use a derived test to execute any other sequences you want to execute during run_phase. You can also use the factory to change the default sequence either via an override in the derived test of via the command line.

Thanks for the suggestions. Could you please explain what uvm_object_wrapper means and when/where it should be used?

4

In reply to UVM_beginner:
See

https://verificationacademy.com/forums/uvm/uvmobjectwrapper#reply-66531

And an example here

https://verificationacademy.com/forums/uvm/problem-parameterized-defines#reply-56243

5

In reply to dave_59:

Thanks, Dave!

6

In reply to dave_59:

Thanks Dave, I have a better idea now based on the use-case example.

7

In reply to tfitz:

Hi,
Please could you give an example for this? "Second, you should not use the uvm_config_db to set the default_sequence for any phase. Instead, you should specify the default sequence to be executed during the run_phase of your base test. "

Do you mean I should use “explicit” sequence execution? I am not sure if you mean “uvm_config_db” is the issue or “reset_phase” is the issue, or both?

Example :
class test_base extends uvm_test;

virtual task main_phase(uvm_phase phase);
seq1 seq;
//raise obj
seq = seq1::type_id::create(“seq”, this);
seq.randomize();
seq.start(env.agt.sqr);
//drop obj
endtask
endclass

If you mean something else, please let me know?

  1. In which case, could you please let me know the disadvantage of using implicit sequence execution?

  2. If implicit sequence execution is okay, but just should not be passed as “default_sequence”, please show me an example of how to use it to specify?

Thanks.