In reply to cgales:
Thank you for the reply. I had tried changing the code to look like this in top file
clk = 1'b1;
#10 clk= ~clk;
this is the interface code
interface man_if(input clk);
`@(posedge clk) `uvm_info("info2","not blocking...",UVM_LOW)
endtask : check_clk
endinterface : man_if
and the display is showing only the first line.
This really is the complete record of clock appearing in the files. I do not own the module I am trying to verify so I am not sure how much I can share
I have another task in the driver run_phase which is executing correctly with @(posedge clk) removed. Is there anything specific you'd like to know?