It is necessary to define separate class of sequencers which is inside the virtual sequence (sequencer handles).or we can use same normal sequencer inside virtual sequence.??
to get the sequencer which is inside the virtual sequencer, we have create separate agent class or we can set it inside normally create agent (i am trying to verify AND_GATE DUT).
In reply to NEHA JAIN:
Can be use the virtual sequences for single interface design, like am using virtual sequences to generate stimulus for AND GATE RTL design, but it is not working?? Please any one can help me
As much as I am able to understand your requirements I tried answering your queries:
Virtual sequence/sequence are independent of interface(ideally), it is the injecting of the vectors you want to drive on the interface through the driver. Generally sequences are athigher abstraction level and driver does that transaction level to signal level communication.
By calling separate class for sequencers in virtual sequence did you create virtual sequencers there ?
Anyway it can be done without that as well , what you all need is handle to sequencer on which you wanted your sequences to run, if you have set the sequencer handle anywhere in your environment(usually we do in top_env) you directly get the same from config_db and assign it to your local instance and thus you have the handle to your sequencer and now you can send any payload you want.
In reply to karandeepsingh:
hey karandeep thanks for your response.
I set the sequencer from env. and get in virtual sequencer. I am using separate sequencer to handle virtual sequencer, but error are not going. I am attaching code please check it once.
//compile errors---------------------
class/and_virtual_seq.sv<13>:Invalid type ‘vitual_seqr’(separate sequencer which I am using )
class/and_virtual_seq.sv<13>:undefined variable ‘vitual_seqr’
class/and_write_test.sv<33>: near"and_write_inst" syntax error : unexpected IDENTIFIER expecting# class/and_write_test.sv<35>:near"and_reset_inst" syntax error : unexpected IDENTIFIER expecting #
//run time error---------------------
uvm_test_top.env_inst.agent_inst.seqr@@seq_inst [uvm_test_top.env_inst.agent_inst.seqr.seq_inst] Response queue overflow, response was dropped
//warning
UVM_WARNING @ 0: uvm_test_top.env_inst.agent_inst.seqr@@seq_inst [uvm_sequence_base] Body definition undefined
//-------------code----------------------------------------
//-------class sequence------------------------------
class and_sequence extends uvm_sequence #(and_transaction);//parameterized with the type of the transaction
`uvm_object_utils(and_sequence) //uvm factory....registration
and_transaction tx; //sequence item
function new(string name =" "); //constructor
super.new(name);
endfunction :new
task body();
endtask:body
endclass :and_sequence
class and_write_seq extends and_sequence;
`uvm_object_utils(and_write_seq)
// data members
and_transaction write_tx;
// constructor
function new (string name="");
super.new(name);
endfunction : new
// body
task body();
// super.body();
`uvm_info("seq_body",$sformatf(" starting and_write_seq "),UVM_LOW)
write_tx = and_transaction::type_id::create("write_tx");
start_item(write_tx);
if(!write_tx.randomize() with {is_data==1; reset==0;})
`uvm_error("seq_body"," write_tx randomization failed")
finish_item(write_tx);
//wait for completion of burst
// get_response(write_tx);
`uvm_info("seq_body",$sformatf(" and_write_seq ends "),UVM_LOW)
endtask : body
endclass : and_write_seq
class and_reset_seq extends and_sequence;
`uvm_object_utils(and_reset_seq)
// data members
and_transaction reset_tx;
// constructor
function new (string name="");
super.new(name);
endfunction : new
// body
task body();
// super.body();
`uvm_info("seq_body",$sformatf(" starting and_reset_seq "),UVM_LOW)
reset_tx = and_transaction::type_id::create("reset_tx");
start_item(reset_tx);
if(!reset_tx.randomize() with {reset==1; is_data==0;})
`uvm_error("seq_body"," reset_tx_req randomization failed")
finish_item(reset_tx);
//wait for completion of burst
// get_response(reset_tx);
`uvm_info("seq_body",$sformatf(" and_reset_seq ends "),UVM_LOW)
endtask : body
//base test-------------------------------------------
class my_base_test extends uvm_test;
`uvm_component_utils(my_base_test) //uvm factory…registration
my_env env_inst;
//and_sequence tx_seq;
//and_sequence seq_inst;
// Configuration objects
env_config env_config_inst;
function new(string name=“my_test”, uvm_component parent=null); //constructor
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
// env configuration
env_config_inst = env_config::type_id::create(“env_config”);
// Create the sequence
// seq_inst= and_sequence::type_id::create(“seq_inst”,this);
// Set the spi env config object
uvm_config_db #(env_config)::set(this, “*”, “env_config_inst”, env_config_inst);
// Create the enviornment
env_inst = my_env::type_id::create(“env_inst”, this);
endfunction:build_phase
endclass :my_base_test
///////////////////////////////////////////////////////////
//------------reset test-------------------------------------------
class my_reset_test extends my_base_test;
`uvm_component_utils(my_reset_test) //uvm factory…registration
//------------------------------------------
// Methods
//------------------------------------------
// Standard UVM Methods:
//function new(string name = “my_reset_test”, uvm_component parent = null);
//function void build_phase(uvm_phase phase);
//task run_phase(uvm_phase phase);
function new(string name=“my_reset_test”, uvm_component parent=null); //constructor
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build(phase);
endfunction:build_phase
task run_phase(uvm_phase phase);
// uvm_info("test",$sformatf(" enter inside run_phase of PUT SEQUENCES ON SEQUENCER "),UVM_NONE); uvm_info(“test”,$sformatf(" enter inside run_phase of my_reset_test "),UVM_NONE);
and_reset and_reset_inst = and_reset::type_id::create(“and_reset_inst”);
// We raise objection to keep the test from completing
phase.raise_objection(this, “Test Started”);
// start sequence put on the sequencer
and_reset_inst.start(null);
`uvm_info(“test”,$sformatf("and_reset seq starting "),UVM_NONE);
// #1000ns;
// uvm_report_info(“”,“Global Request”, UVM_LOW);
// global_stop_request();
// We drop objection to allow the test to complete
phase.drop_objection(this, “Test Finished”);
`uvm_info(“test”,$sformatf("and_reset seq ending "),UVM_NONE)
endtask :run_phase
function void end_of_elaboration();
print();
endfunction : end_of_elaboration
endclass :my_reset_test
//---------------------------write test
//------------test-------------------------------------------
class my_write_test extends my_base_test;
`uvm_component_utils(my_write_test) //uvm factory…registration
//------------------------------------------
// Methods
//------------------------------------------
// Standard UVM Methods:
//extern function new(string name = “my_write_test”, uvm_component parent = null);
//extern function void build_phase(uvm_phase phase);
//extern task run_phase(uvm_phase phase);
function new(string name=“my_write_test”, uvm_component parent=null); //constructor
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build(phase);
endfunction:build_phase
task run_phase(uvm_phase phase);
`uvm_info(“test”,$sformatf(" enter inside run_phase of my_write_test "),UVM_NONE);
and_write and_write_inst = and_write::type_id::create(“and_write_inst”);
// We raise objection to keep the test from completing
phase.raise_objection(this, “Test Started”);
// start sequence put on the sequencer
and_write_inst.start(null);
`uvm_info(“test”,$sformatf("and_write seq starting "),UVM_NONE);
// #1000ns;
// uvm_report_info(“”,“Global Request”, UVM_LOW);
// global_stop_request();
// We drop objection to allow the test to complete
phase.drop_objection(this, “Test Finished”);
`uvm_info(“test”,$sformatf("and_write seq ending "),UVM_NONE)
endtask :run_phase
function void end_of_elaboration();
print();
endfunction : end_of_elaboration
endclass :my_write_test
//----------Vitual sequencer--------------------------------
class virtual_seqr extends uvm_sequencer#(and_transaction);
`uvm_component_utils(virtual_seqr) //uvm factory....registration
function new(string name = "virtual_seqr", uvm_component parent=null); //constructor
super.new(name,parent);
endfunction
endclass:virtual_seqr
//-----------------------------------------------Virtual sequences
class and_vseq_base extends uvm_sequence #(uvm_sequence_item);
`uvm_object_utils(and_vseq_base)
function new(string name = “and_vseq_base”);
super.new(name);
endfunction
// Virtual sequencer handles
virtual_seqr virtual_seqr_inst;
// Handle for env config to get to interrupt line
//and_env_config m_cfg;
// This set up is required for child sequences to run
task body;
// virtual_seqr_inst = virtual_seqr::type_id::create(“virtual_seqr_inst”);
if(!uvm_config_db #(virtual_seqr)::get(null, get_full_name(), “virtual_seqr”, virtual_seqr_inst)) begin
`uvm_error(“CONFIG_DB_ERROR”, “and sequencer not found”)
end
/* if(!uvm_config_db #(and_env_config)::get(null, {“uvm_test_top.”, get_full_name()}, “and_env_config”, m_cfg)) begin
`uvm_error(“body”, “Cannot find and_env_config”)
end */
endtask: body
endclass: and_vseq_base
// single and reset seq with random data
class and_reset extends and_vseq_base;
`uvm_object_utils(and_reset)
function new(string name = “and_reset”);
super.new(name);
endfunction
task body;
// issue reset seq
and_reset_seq reset_seq = and_reset_seq::type_id::create("reset_seq");
//call base virtual seq for sequencer's handle and cfg onject
// super.body;
//start tx and rx sequences
fork
//at and_agent
reset_seq.start(virtual_seqr_inst);
join
endtask: body
endclass: and_reset
// single and reset seq with random data
class and_write extends and_vseq_base;
`uvm_object_utils(and_write)
function new(string name = “and_reset”);
super.new(name);
endfunction
task body;
// issue reset seq
and_write_seq write_seq = and_write_seq::type_id::create("write_seq");
// virtual_seqr_inst=virtual_seq::type_id::create(.name(virtual_seq),.parent(this));
//call base virtual seq for sequencer's handle and cfg onject
// super.body;
//start and_write sequences
fork
//at and_agent
write_seq.start(virtual_seqr_inst);
join
endtask: body
endclass: and_write
//--------------------------------------------------------------end virtual_seq-------------
//*********************************************************
// Class env
//*********************************************************
class my_env extends uvm_env;
//*********************************************************
// Register class env in uvm factory
//*********************************************************
`uvm_component_utils(my_env)
//*********************************************************
// Create Instance of environment configuration
//*********************************************************
env_config env_config_inst;
//*********************************************************
// Create Instance of agent
//*********************************************************
my_agent agent_inst;
//*********************************************************
// Create Instance of coverage
//*********************************************************
my_fc_sb my_fc_sb_inst;
//*********************************************************
// Create Instance of scoreboard
//*********************************************************
my_sb my_sb_inst;
//*********************************************************
// Construction Method
// Parent is the object in which environment is instantiated
//*********************************************************
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
//*********************************************************
// Build Method
//*********************************************************
function void build_phase( uvm_phase phase );
super.build_phase( phase );
//*********************************************************
// Construct environment configure
//*********************************************************
uvm_report_info(“”,“Creating Environment Configration…”, UVM_LOW);
env_config_inst = env_config ::type_id::create ( “env_config_inst” );
//*********************************************************
// Construct Agent
//*********************************************************
if ( env_config_inst.en_agent ) begin
uvm_report_info(“”,“Creating Agent…”, UVM_LOW);
agent_inst = my_agent::type_id::create( .name( “agent_inst” ), .parent( this ) );
end
//*********************************************************
// Construct Scoreboard
//*********************************************************
if ( env_config_inst.en_sb ) begin
uvm_report_info(“”,“Creating Scoreboard…”, UVM_LOW);
my_sb_inst = my_sb::type_id::create( .name( “my_sb_inst” ), .parent( this ) );
end
//*********************************************************
// Construct Coverage
//*********************************************************
if ( env_config_inst.en_fc_sb ) begin
uvm_report_info(“”,“Creating Subscriber…”, UVM_LOW);
my_fc_sb_inst = my_fc_sb::type_id::create( .name( “my_fc_sb_inst” ), .parent( this ) );
end
endfunction: build_phase
//*********************************************************
// Connect Method
//*********************************************************
function void connect_phase( uvm_phase phase );
super.connect_phase( phase );
//*********************************************************
// Connecting Agent and Coverage(TLM port to export)
// analysis port[agent] <—> analysis export[subscriber]
//*********************************************************
if ( env_config_inst.en_agent && env_config_inst.en_fc_sb)
uvm_report_info(“”,“Connecting Agent and Subscriber…”, UVM_LOW);
agent_inst.ap.connect( my_fc_sb_inst.analysis_export );
//*********************************************************
// Connecting Agent and scoreboard
// analysis port[agent] <—> analysis export[subscriber]
//*********************************************************
if ( env_config_inst.en_agent && env_config_inst.en_sb)
uvm_report_info(“”,“Connecting Agent and Scoreboard…”, UVM_LOW);
agent_inst.ap.connect( my_sb_inst.analysis_export );
// Set up the agent sequencers as resources:
// uvm_config_db #(tx_rmmi_sequencer)::set(null, “", “tx_rmmi_sequencer”, m_tx_rmmi_agent.m_sequencer);
uvm_config_db #(virtual_seqr)::set(null, "”, “virtual_seqr”, agent_inst.virtual_seqr_inst);
endfunction: connect_phase
//*********************************************************
// End Of Elaboration Method
// In this method, call the print() method. This print()
// method will print the topology of the test
//*********************************************************
function void end_of_elaboration();
uvm_report_info(“”,“End_of_elaboration”, UVM_LOW);
endfunction
//*********************************************************
// Start Of Simulation
//*********************************************************
function void start_of_simulation();
uvm_report_info(“”,“Start_of_simulation”, UVM_LOW);
endfunction
task run_phase(uvm_phase phase);
uvm_report_info(“”,“Run Env”, UVM_LOW);
endtask
//*********************************************************
// Extract Method
//*********************************************************
function void extract();
uvm_report_info(“”,“Extract”, UVM_LOW);
endfunction
//*********************************************************
// Check Method
//*********************************************************
function void check();
uvm_report_info(“”,“Check”, UVM_LOW);
endfunction
//*********************************************************
// Report Method
//*********************************************************
function void report();
uvm_report_info(“”,“Report”, UVM_LOW);
endfunction
endclass
//------------------------end env---------------------------------------
//------------------------------agent------------------------------------
//-----------------------agent-----------------------
// The agent contains sequencer, driver, and monitor (not included)
class my_agent extends uvm_component;
`uvm_component_utils(my_agent)
//*********************************************************
// Create Instance of analysis port
//*********************************************************
uvm_analysis_port #(and_transaction) ap;
//*********************************************************
// Create Instance of agent configuration
//*********************************************************
agent_config agent_config_inst;
//*********************************************************
// Create Instance of Sequencer
//*********************************************************
my_seqr seqr;
//*********************************************************
// Create Instance of Sequencer
//*********************************************************
virtual_seqr virtual_seqr_inst;
//*********************************************************
// Create Instance of Driver
//*********************************************************
my_driver drv;
//*********************************************************
// Create Instance of Monitor
//*********************************************************
my_monitor monitor;
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction
//*********************************************************
// Build Method
//*********************************************************
function void build_phase(uvm_phase phase);
super.build_phase(phase);
//*********************************************************
// Construct analysis port
//*********************************************************
uvm_report_info(“”,“Creating Agent Analaysis Port…”, UVM_LOW);
ap = new(“ap”, this);
//*********************************************************
// Construct agent configuration
//*********************************************************
uvm_report_info(“”,“Creating Agent Configuration…”, UVM_LOW);
agent_config_inst = agent_config::type_id::create( .name( “agent_config_inst” ), .parent( this ) );
//*********************************************************
// Check agent configuration = ACTIVE
// Construct Driver and Sequencer
//*********************************************************
if ( agent_config_inst.active == UVM_ACTIVE )
begin
uvm_report_info(“”,“Creating Driver and Sequencer…”, UVM_LOW);
drv = my_driver::type_id::create(“drv”, this);
seqr = my_seqr::type_id::create(“seqr”, this);
virtual_seqr_inst = virtual_seqr::type_id::create(“virtual_seqr_inst”, this);
end
//*********************************************************
// Construct Monitor
// Agent Configuration = ACTIVE OR PASSIVE
//*********************************************************
uvm_report_info(“”,“Creating Monitor…”, UVM_LOW);
monitor = my_monitor::type_id::create( .name( “monitor”), .parent( this ) );
endfunction: build_phase
//endfunction : build_phase
//*********************************************************
// Connection Method
//*********************************************************
// In UVM connect phase, we connect the sequencer to the driver.
function void connect_phase(uvm_phase phase);
//*********************************************************
// Connecting Agent and Monitor(TLM port - port)
// analysis port[agent] <—> analysis port[monitor]
//********************************************************
uvm_report_info(“”,“Connecting Agent and Monitor…”, UVM_LOW);
ap = monitor.ap;
//*********************************************************
// Check agent configuration = ACTIVE &
// Connecting Driver and Sequencer (TLM port - export)
// seq_item_port[driver] <—> seq_item_export[sequencer]
//*********************************************************
if ( agent_config_inst.active == UVM_ACTIVE ) begin
uvm_report_info(“”,“Connecting Driver and Sequencer…”, UVM_LOW);
drv.seq_item_port.connect(seqr.seq_item_export);
end
endfunction :connect_phase
/*
task run_phase(uvm_phase phase);
// We raise objection to keep the test from completing
phase.objection.start(this);
begin
and_sequence sequenc;
sequenc= and_sequencer::type_id::create(“sequenc”,this);
sequenc.start(seqr);
end
// We drop objection to allow the test to complete
phase.objection.drop(this)
*/
endclass
//--------------------------end agent------------------------------------------------